Part Number: UCD90120A
Hi TI team,
I have a question about sequence design by rail configuration. You can see the relevant settings in attached .XML file I provided.
After verfication, my settings can achieve correct power-up sequence as I expected. P3V3(Rail1) ---> ROV_CORE(Rail2) ---> 0V8_CORE(Rail3).
But I found an unepxected behavior on enable control when I turened off P3V3 manually. The enable pin of ROV_CORE(Rail2) and 0V8_CORE(Rail3) still keep high level even P3V3(Rail1) off.
According to my understanding, the enable function can't work normally if previous criterion(voltage threshold) is not true.
Could you help to check which settings are incorrect ?
Thanks.
Blake
(Please visit the site to view this file)