Part Number: TMS320F280049
In the TRM, there might be sth wrong for the description of ADCINTFLGCLR register. Could you help check which one is the right one?
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1 Clears respective flag bit in the ADCINTFLG register. If software
sets the clear bit on the same cycle that hardware is trying to set the
flag bit, then hardware has priority but the overflow bit will not be
affected (retains current state)
Boundary condition: If hardware is trying to set the bit flag while
software tries to clear the bit in the same cycle, the following will take
place:
1. SW has prioirity and will clear the flag
2. HW set will be discarded
no signal will propagate to the PIE from the latch
3. Overflow flag/condition will be generated