Part Number: LM3481
Tool/software: WEBENCH® Design Tools
Hi,
I am trying to design Sepic converter using LM3481 with the below sepicifications. I did simulation in Pspcie tool. Also find the attached diagram of Simulation
Input range - 6V-32V
Output Voltage - 15.5V
Load current - 0 - 2.25 A
Rsen = 10mOhms
Query 1: Unable to get the same simulation results (Pspice) when compared with TI Webench?
Query 2: Unable to get 15.5V output voltage on No-load condition, it exceeds 17.7V. How to maintain 15.5V on No-load?
Query 3: Unable to load the converter with 90% or full load when my Input is around 8V? Voltage loop becomes unstable.
Query 4: Also need to run the simulation at faster rate in Pspice. Used SS=1, Vcomp={{VOUT}*{IOUT}*{RSEN}/{VIN}}
If you need any information for analysis, please let me know