Hi,
I have a few question about DM368 DDR2.
We are having a CPU exception problem caused by DDR2 write/read access
while doing audio encode process.
When reading 32bytes data from DDR2, the first 4byte data was not expected value.
The next 4 bytes was data which should be read first and after that
it keeps reading 4byte front of the appropriate data.
Is this DDR2 Read latency problem ?
So, do you think it might be solved by setting appropriate value to DDRPHYCR1 register?
Or is there any other factor to cause this problem like if DQGATE Length didn't match to
the "CK net plus the average length of the DQS0 and DQS1 nets"?
Another question is about DDR2 PBBPR(Peripheral Bus Burst Priority Register).
In DDR2 User's Guide page.53 "Note", it said that you must change the default value other than 0xFF.
What kind of value should I set to the PBBPR.PR_OLD_COUNT?
best regards,
g.f.