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CCS: CPU TIMER0 for sine generation and TIMER1 for Adc triggering

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Tool/software: Code Composer Studio

Hello,

I am I am generating sine wave of 1000 points because my switching frequency is 50KHz and fundamental frequency is 50Hz so 50KHz/50Hz=1000, so I  use CPU TIMER0 interrupt to for sine wave generation and CPU TIMER1 for adc triggering.

1. CPU TIMER0: 1/50KHz = 20us    //50Khz is switching frequency  when I put 20us then sine wave is not right but when I put 20000us  which is 1/50Hz =20ms . could you please tell me which one is right either 1/50KHz or 1/50Hz

ConfigCpuTimer(&CpuTimer0, 200, 20);

2. CPU TIMER1: is used to trigger ADC, I don't know which time period I should write in CPU TIMER1 according to my switching frequency 50 KHz  and do I need CPU TIMER1 ISR ? or I just need to configure CPU TIMER1 and set TRIGSEL = 2 is enough for ADC triggering

ConfigCpuTimer(&CpuTimer1, 200, 20000);

CpuTimer1Regs.TCR.all = 0x4000;

I am attaching my code please see if there are mistakes

 

voidmain(void)

{

InitSysCtrl();

InitEPwm2Gpio();

/******Voltage PI Regulator*****/

CNTL_PI_F_init(&VC);

VC.Ki = (500);

VC.Kp = (5);

VC.Umax= 10;

VC.Umin= -10;

/******Current PI Regulator*****/

CNTL_PI_F_init(&IL);

IL.Ki = (6000);

IL.Kp = (0.005);

IL.Umax= 30;

IL.Umin= -30;

DINT;

InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;

IFR = 0x0000;

InitPieVectTable();

EALLOW;

PieVectTable.TIMER0_INT = &cpu_timer0_isr;

PieVectTable.EPWM2_INT = &epwm2_isr;

EDIS;

EALLOW;

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;

EDIS;

InitEPwm2Example();

ConfigureADC();

SetupADCEpwm();

EALLOW;

CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;

EDIS;

PieCtrlRegs.PIEIER3.bit.INTx2 = 1;

IER |= M_INT3;

InitCpuTimers();

ConfigCpuTimer(&CpuTimer0, 200, 20000);//

ConfigCpuTimer(&CpuTimer1, 200, 20000);//

CpuTimer0Regs.TCR.all = 0x4000;

CpuTimer1Regs.TCR.all = 0x4000;

IER |= M_INT1; //Enable group 1 interrupts

PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

PieCtrlRegs.PIEIER1.bit.INTx7 = 1; //Timer0 interrupt is directly connected to group INT1, Bit7

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

EINT;

ERTM;

// Enable global Interrupts and higher priority real-time debug events:

EINT; // Enable Global interrupt INTM

ERTM; // Enable Global realtime interrupt DBGM

}

interruptvoidepwm2_isr(void)

{

//Samlped voltage and current

i1=((float)(AdcaResultRegs.ADCRESULT1)-2210)*0.01;

v1=((float)(AdcaResultRegs.ADCRESULT3)-2192)*0.0364;

ia[0]=ia[1];

ia[1]=ia[2];

ia[2]=(ia[0]+ia[1]+i1)/3;

 

vo[0]=vo[1];

vo[1]=vo[2];

vo[2]=(vo[0]+vo[1]+v1)/3;

 

/*****voltage PI Regulator*****/

VC.Ref=a;

VC.Fbk=vo[2];

CNTL_PI_F_FUNC(&VC);

/*****Current PI Regulator*****/

IL.Ref=VC.Out;

IL.Fbk= ia[2];

CNTL_PI_F_FUNC(&IL);

d=IL.Out;

 

SPWM(d,100,0,0,0);

EPwm2Regs.ETCLR.bit.INT = 1;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

}

voidInitEPwm2Example()

{

//

// Setup TBCLK

//

EPwm2Regs.TBPRD = PERIOD ; // Set timer period

EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0

EPwm2Regs.TBCTR = 0x0000; // Clear counter

//

// Setup counter mode

//

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT

EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync output is equal to zero

//

// Setup shadowing

//

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//

// Setup compare

//

EPwm2Regs.CMPA.bit.CMPA = 0; //

//

// Set actions

//

EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // EPW1A

EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // EPW1A

EPwm2Regs.AQCTLB.bit.CAD = AQ_CLEAR; // EPW1B

EPwm2Regs.AQCTLB.bit.CAU = AQ_SET; // EPW1B

//

// Interrupt where we will change the Compare Values

//

EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event INTSEL= interrupt selection

EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT

EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

 

 

//Start Conversion of ADC

EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group

EPwm2Regs.ETSEL.bit.SOCASEL = 2;

EPwm2Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event

}

voidConfigureADC(void)

{

EALLOW;

//

//write configurations

//

AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /2

AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);

//

//Set pulse positions to late

//

//

//

AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//

//power up the ADC

//

AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;

//

//delay for 1ms to allow ADC time to power up

//

DELAY_US(1000);

EDIS;

}

//

// ConfigureEPWM - Configure EPWM SOC and compare values

//

 

 

//

// SetupADCEpwm - Setup ADC EPWM acquisition window

//

voidSetupADCEpwm(void)

{

//

//Select the channels to convert and end of conversion flag

//

EALLOW;

AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;

AdcaRegs.ADCSOC1CTL.bit.ACQPS = 28;

AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 2;

 

AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;

AdcaRegs.ADCSOC3CTL.bit.ACQPS = 28;

AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 2;

//

//Intrupt

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0;

AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1;

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

EDIS;

}

interruptvoidcpu_timer0_isr(void)

{

if(num<1000)

{num++;}

else

{num=0;}

z=2*3.14*num/1000;

a=30*sinf(z);

 

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}

voidSPWM(float Ea,float DC,int ISA_DIRECTION,int ISB_DIRECTION,int ISC_DIRECTION )

{

float CMP;

CMP=HALF_PERIOD+Ea*0.6;

EPwm2Regs.CMPA.bit.CMPA =(Uint16)CMP;

}



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