I have a question about the SD24_A 24-bit delta sigma ADC in the MPS430AFE2xx family. Specifically, I am working with the MSP430AFE253.
I understand that the maximum SNR is 90dB, meaning I shouldn't expect more than 14 bits of noise-free output regardless of my external circuitry. However, I have seen mentioned in several other threads on this forum that one of the benefits of this type of ADC is that the noise floor will move with the signal level. Essentially, this should give me (again, at best) 14 significant bits down from the first set bit.
Now, I have been testing this out and I cannot get significant bits from lower than the 14th (absolute) bit of the SD24MEM0 register. Meaning, I am not seeing the behavior where the noise floor is decreasing with the signal level. Even when I set SD24INCH0 to 7, shorting the inputs internally, I still see flipping of the 14th or 15th (absolute) bit.
Below are the details of my configuration, perhaps there is a setting I am missing? Am I assuming incorrectly that the very small offset voltage measured when the ADC inputs are internally shorted should result in a more precise measurement?
If anybody has any ideas, I would much appreciate them.
-Drew
Configuration Details
- MSP430AFE253, programmed and interfaced with the MSP-TS430PW24 target board
- MCLK from DCO at 12MHz, SMCLK = MCLK/4 (3MHz), SD24 CLK = SMCLK/3 (1MHz)
- Internal 1.2V reference turned on and stabilized for ~5ms
- OSR = 1024
- SD24MEM0 is 2's complement format non-unidirectional and the LSB Toggle is enabled to allow reading all 30 bits of the digital filter output
- PGA Gain = 1
- input channel = A0.0.
The following is the code to A) read from the digital filter and B) convert that to a 24-bit digital value
A)
ADC_Buffer[0] = SD24MEM0; // First read is MSWord
ADC_Buffer[1] = SD24MEM0; // Second read is LSWord
B)
*ResponsePtr = ADC_Buffer[0]; // First 16 bits are bits [29:14] of the digital filter output
*ResponseBytePtr2 = ADC_Buffer[1] >> 6; // Last 8 bits are bits [13:6] of the digital filter output