Hello,
I am having some issues getting my release build to run on my C6748.
I have many different compiler settings and have even made my release configuration settings match my debug settings completely (turned off optimization, turned debug features on). The part in my program that the release mode gets stuck in is this while loop:
// Program the RATIO fields for each PLLDIV and disable unused clocks
PLL0_PLLDIV1 = 0x8000; // Fixed ratio /1 -> ( 1 / (0+1) ) = 1:1 // 300Mhz (Max: 375Mhz)
PLL0_PLLDIV2 = PLL0_PLLDIV1 + 1; // Fixed ratio /2 -> ( 1 / (1+1) ) = 1:2 // 150Mhz (Max: 187.5Mhz)
PLL0_PLLDIV3 = 0x0002; // Variable ratio /3 -> Disabled. No EMIFA.
PLL0_PLLDIV4 = PLL0_PLLDIV1 + 3; // Fixed ratio /4 -> ( 1 / (3+1) ) = 1:4 // 75Mhz (Max: 93.75Mhz)
PLL0_PLLDIV5 = 0x0002; // Variable ratio /3 -> Disabled. Not used on chip.
PLL0_PLLDIV6 = 0x0000; // Fixed ratio /1 -> Disabled. Not used on chip.
PLL0_PLLDIV7 = PLL0_PLLDIV1 + 5; // Variable ratio /6 -> ( 1 / (5+1) ) = 1:6 // 50Mhz (Max: 50Mhz)
// Set the GOSET bit (b0) in PLLCMD high to initiate a new divider transition
setBit( &PLL0_PLLCMD, 0 );
// Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).
while( getBit( &PLL0_PLLSTAT, 0 ) == HIGH )
{
// Do nothing
}
This should be familiar, as it is part of the common gel script initialization routine. I removed the dependency on gel scripts and put all of my initialization code in the program itself. I have tried putting delays all around, before, within, and after this while loop and the other parts of the this initialization routine before it gets called, thinking that the release mode may be executing too fast, but that made no difference. My routine follows that described by the reference manual for this exact chip exactly.
Does anyone have any suggestions or advice?
Thanks
Charles