Part Number:ADS52J90
This is a follow up question regarding the length matching of the JESD CML signals between the ADC and FPGA. This was not really answered in the previous post and I would like some clarification.
JESD204B does not require length matching between the differential lanes. This is one benefit of the protocol.
Is this not the case for ADS52J90? Does it require the lanes to be length matched?