We're currently using a 6670, and are testing Data transfers and Memory using the EDMA, however it is randomly stopping, where the transfer is set, however the transfer and interrupt never happens.
Here are some details on what's happening and how we have it setup
- It works fine when using just one core, multiple core use is when we run into problems
- It works fine most of the time when using larger transfers (2MB) but runs into the problem often when using smaller transfer sizes (1k)
- It is setup on TCC0
- Each core is copying to and from different memory locations (no overlap)
- Each core uses a different channel (0-4)
- Each core uses a different shadow region (0-4)
- Each core generates a different EDMA interrupt (0-4)
Not exactly sure what is happening, any help, suggestions would be greatly appreciated.
Erick