Part Number:TCAN4550-Q1
I’m having difficulty with the TCAN4550 and I’m not quite sure what’s going on… I’m basically trying to send an 8 byte command from the Aggregator Board over to the Control Board. When the Control Board receives the message, it responds with a 32 byte message.
I have the following I/O lines set for the listed conditions.
Right after the TCAN4550 on the Aggregator and Control Board are initialized, the operation works perfect. I see the I/O line operate on both boards as expected and both boards are receiving the messages correctly. The problem occurs on the 2nd iteration of this same operation.
On the Aggregator side, I’m trying to send the same message over to the Control Board but the Control Board never Acknowledges.
Here is what I’m seeing:
1st Operation (Works successfully)
Aggregator Control Board
Reading 0x10C4, the Index returns a 0
8 byte message is sent out of TXBuffer 1 of 5
GPO2 transitions low GPIO1 transitions low
Write a 0x00000001 back into 0x1050 to clear the interrupt.
Reinitializes the uC IO line and clears bit 9 in 0x1050 Control Board pulls message out of RX Buffer
Writes Index back into 0x10A4 to Acknowledge
Compiles 32 byte message
Transmits 32 byte message
GPIO1 transitions low indicating new message
Write a 0x00000001 back into 0x1050 to clear the interrupt
Aggregator pulls message out of FIFO0
Writes index back into 0x10A8 to Acknowledge
2nd Operation (Does Not work)
Aggregator Control Board
Using the same 8 byte message
Reading 0x10C4, the Index returns a 1
8 byte message is sent out of TXBuffer 2 of 5
GPO2 remains HIGH GPI01 remains HIGH
8 byte message is sent continuously
I’ve followed the TX and RX procedures, too the letter, in “TCAN4x5x Software User’s Guide” but something is not working correctly. During the 2nd operation, the message is being sent but the GPO2 line of the Aggregator doesn’t toggle to indicate the Transmission is Complete and the Control Board is not receiving it correctly. (I validated that the message is exactly the same)
I’ve got a couple of questions about the operation:
Does the TX Complete Interrupt only occur after the Message is Acknowledged?
Other than the write back into 0x10A4 and 0x1050, what would prevent the reception of the 2nd Transmission if the Control Board has 5 RX FIFOs for receiving?
I've noticed when reading register 0x1050 that multiple Interrupt flags are set even though they are cleared at initialization. Why would multiple flags be set when my setup configures the interrupts for RX New Message and TX Complete?
Thanks for your help,
Joe Cely