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Linux/66AK2G12: Difficulty validating RGMII timing with DP83867 PHY

Part Number:66AK2G12

Tool/software: Linux

Hello,

As mentioned in the "related post" (Image may be NSFW.
Clik here to view.
) I have been working on a design using the 66AK2G12 and DP83867.  We had a significant number of changes between the prototype run and our first production units.  In the process of bringing up these units, I have run into the problem where Ethernet works at 100Mb but does not work at 1Gb.  Since this issue was previously solved by adjusting timing settings, I have begun to dig into the timing on these units.  These measurements are at the edge of what my scope can read, but snla243.pdf suggests that it should be sufficient.  I am able to see clock and data on the RX side of the RGMII bus, but I do not see any data traffic on the TX side when running at 1Gb.  I do, however, see data going both ways when running at 100Mb.  I have been able to measure the timing of the RX bus and adjust it so that setup and hold are within limits, but since I see no traffic on the TX side, it is difficult to validate the timing.

Relevant info:
Processor SDK Linux 5.1
PHY is being clocked off of CLKOUT @ 25MHz
Device Tree for ethernet phy, mdio, etc matches DTS for K2G ICE, which uses this phy.
Trace lengths of all RX/TX signals are well matched with each other (<15 mils)
Ethernet CLKCTL is set such that CLKOUT puts out a 25MHz clock
Ethernet CFG is set such that the mode is RGMII.  I have tried enabling and disabling IDELAY as part of my timing experiments.
Occasionally, U-Boot is able to secure a DHCP lease.  When this happens, no further transfers can be made.
Sometimes DHCP requests can be seen on a Wireshark capture.  This is not consistent or easily reproduced.
I have had to modify U-Boot from the reference design to eliminate the board detection code.

Please let me know what other information is needed so that we can figure this out.

Jeff


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