I am trying to connect an ML605 Xilinx FPGA dev kit (which contains a SRIO IP core) with the TMDSEVM6670LE Rev 3a. Link bring-up runs correctly, I can exchange MAINTENANCE packets, and I see no errors in SPn_ERR_STAT. However, when I try to send a MESSAGE packet to the DSP, I get an ILL_TRANS_DECODE error and the socket (which is blocking) never unblocks.
My RXU_MAP settings (I use only one rule) are very loose and I barely set any masks. Still, I am getting the access block and I wonder if it could be due to a malformed packet. Since I cannot read what is being sent by the FPGA kit, I would like to know what could cause the peripheral to trigger this error. Maybe a reserved SrcID or DstID; maybe Segment Mapping must be matching? Please list all the cases, it will greatly improve my understanding of the matter.