PCM1864 - Generating BCLK and LRCLK from PLL clock in master mode.

Hello TI Experts,

I've been playing around with a PCM1864 for the last few days, and the basics seems to be in place by now. One question still remains though, how do I configure the MUXes, shown in the 'master mode only' section of the Clock tree, to use the PLL as clock source for BCK and LRCK out?

The hardware seems to be in place, but there's no mentioning of the MUXes in the documented registers. Did I miss something or does the datasheet still need some work?

Any help would be appreciated.

regards

Allan