TMS320C6746: EDMA transfer speed from asynchronous EMIF interface

Part Number:TMS320C6746

I am looking for ways to improve the EDMA throughput from the asynchronous EMIF interface on my TMS320C6746 design.  I am observing EMIF timing that I cannot explain.

Here is some information on my setup.

EDMA

Transfer 512 words from EMIF FIFO (fixed address) to IRAM buffer

OPT =

CSL_FMKT (EDMA3CC_OPT_ITCCHEN, DISABLE) |  // Disable intermediate TC chaining

   CSL_FMKT (EDMA3CC_OPT_TCCHEN, DISABLE) |   // Disable final TC chaining

   CSL_FMKT (EDMA3CC_OPT_ITCINTEN, DISABLE) | // Disable intermediate TC interrupts

   CSL_FMKT (EDMA3CC_OPT_TCINTEN, ENABLE) |   // Enable final TC interrupts

   CSL_FMK (EDMA3CC_OPT_TCC, myTCCVal) |

   CSL_FMKT (EDMA3CC_OPT_TCCMOD, NORMAL) |     // Set TCC after the data is transferred

   CSL_FMKT (EDMA3CC_OPT_FWID, RESETVAL) |     // FIFO option not usable

   CSL_FMKT (EDMA3CC_OPT_STATIC, NORMAL) |     // Allow updates to the parameter set

   CSL_FMKT (EDMA3CC_OPT_SYNCDIM, ABSYNC) |   // Transfer 512 by 4 bytes per event

   CSL_FMKT (EDMA3CC_OPT_DAM, INCR) |

   CSL_FMKT (EDMA3CC_OPT_SAM, INCR);

SRC =

MY_EMIF_FIFO_ADDRESS;                      // Transfer from the EMIF FIFO

A_B_CNT =

CSL_FMK (EDMA3CC_A_B_CNT_BCNT, 512) |     // 512 values per transfer

   CSL_FMK (EDMA3CC_A_B_CNT_ACNT, 4);        // 4 bytes per frame

DST =

MY_IRAM_BUFFER;                            // EDMA destination

SRC_DST_BIDX =

   CSL_FMK (EDMA3CC_SRC_DST_BIDX_DSTBIDX, 4) | // increment destination

   CSL_FMK (EDMA3CC_SRC_DST_BIDX_SRCBIDX, 0); // constant source address

CCNT =

CSL_FMK (EDMA3CC_CCNT_CCNT, 1);            // 1 transfer

EMIF

16-bit interface to a 32-bit FIFO

EMA_CLK is 100 MHz

CE3CFG =

   CSL_FMKT (EMIFA_CE3CFG_SS, SELSTRB_ENABLE) |   // Enable strobe mode

   CSL_FMKT (EMIFA_CE3CFG_EW, EXT_WAIT_DISABLE) | // Disable extended wait cycles

   CSL_FMK (EMIFA_CE3CFG_W_SETUP, 0) |             // Write Setup is 1 EMA_CLK cycle

   CSL_FMK (EMIFA_CE3CFG_W_STROBE, 2) |           // Write Strobe is 3 EMA_CLK cycles

   CSL_FMK (EMIFA_CE3CFG_W_HOLD, 0) |             // Write Hold is 1 EMA_CLK cycle

   CSL_FMK (EMIFA_CE3CFG_R_SETUP, 0) |             // Read Setup is 1 EMA_CLK cycle

   CSL_FMK (EMIFA_CE3CFG_R_STROBE, 1) |           // Read Strobe is 2 EMA_CLK cycles

   CSL_FMK (EMIFA_CE3CFG_R_HOLD, 0) |              // Read Hold is 1 EMA_CLK cycle

   CSL_FMK (EMIFA_CE3CFG_TA, 2) |                 // 3 EMA_CLK cycles between reads and writes

   CSL_FMKT (EMIFA_CE3CFG_ASIZE, 16BIT);           // 16-bit Data Bus

During the EDMA transfer, I am monitoring the EMA_OE pin with an oscilloscope. Each FIFO read is two 16-bit transactions. I see this on the oscilloscope as EMA_OE active low for 2 EMA_CLK cycles (strobe), with 2 EMA_CLK cycles (hold and setup) between the reads to complete the 32-bit transaction (EDMA A count).

Between each IFIO read (next EDMA B count), I observe 13 EDMA_CLK cycles. I am having trouble determining what is driving these 13 cycles. I would expect 2 cycles, one for hold and one for setup.