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CCS/TMS320F2806: Working process of the SCI FIFO reception

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Part Number:TMS320F2806

Tool/software: Code Composer Studio

Hi,

I am working with UART communications between two DSPs in a custom board. One is constantly sending SCI messages (master) and the other reading them (slave). I send 4 messages and then generate an interruption in the reception (slave).

How does the reception buffer work? Because while I am reading a given pack of 4 data, the sender is already sending a new pack of 4 so are these new packages queing?

If for any reason I am slower reading than sending will they pile up?

Best regards.


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