Hello all,
I am trying to ensure my I2C communication is as robust as possible. In particular, I am now looking at a case where a Master MSP430 communicates with multiple slave devices. I am considering the case when one or more slaves holds the SDA line low, causing the I2C line to become stuck.
Let's first assume there is only one slave device. If I am using a USCI_B interrupt-driven system, I believe I can do the following: I can set UCNACKIE. In the case that the SDA line is held low, UCNACKIFG will be set, and the code will enter the corresponding ISR. Here, if the MSP430 sends a stop sequence, this should free up the SDA line (is this true, or is there a more elegant solution to this). After this, I could restart another I2C transmission with the slave device since the previous transaction was corrupted.
Let's complicate things a bit further, and say that we are reading a series of registers from the slave. If this is the case, the I2C transmission will be the following:
1) Send address byte with write bit
2) Send register byte (indicating the register to start reading from on the slave device)
3) Send address byte with read bit
4) Keep reading bytes that come from slave until the Master MSP430 sends a NACK (or equivalently, when the MSP430 sends a stop)
Now the question comes, how much of a difference would it make if an error happened in one place versus another -- that is, for example if an error happened before the slave sends the data to the Master MSP430, versus during the transfer of this data? Would the fix be different? Am I correct to assume that this situation could happen, or is it very unlikely to happen in one case versus another.
Sincerely,
Mehdi