Hi all,
I'm having problems booting from NAND ...
We have a custom board with an MT29F8G16 (Micron 8 Gbit, 16-bit wide). Datasheet is attached. It has 256kB erasesize, 4kB pagesize, with 224 spare bytes. (U-boot calculates "oobsize" as 128 bytes.) I have modified the GPMC_NAND_HW_BCH8_ECC_LAYOUT according to:
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/231420/812506.aspx#812506
Even though oobsize is wrong, this change lets me write images to NAND using u-boot, and read them back out, without marking any bad blocks. Using u-boot's crc32 indicates that the data is stored and retrieved correctly. However, I have not been able to actually boot from NAND.
The Micron datasheet says that it is ONFI compliant, but when I log the kernel's attempt to read 'O','N','F','I' from READID/0x20, I just get the READID/0x00 data (0x2C 0xC3 0x90 0xE6). So I guess that the DM814x ROM code gets the same failure, and checks the look-up table. Device ID 0xC3 is in the Supported NANDDevices table in the DM814x TRM (table 4-14). And, there is an 0xC3 entry in the table in u-boot, named "NAND 1GiB 3,3V 16-bit".
For NAND boot, I have been using BTMODE[4:0] = 10010. This gives me the CCCCC from when our board tries the uart boot. If I use TeraTerm to xmodem-send the u-boot.min.nand image, then it starts and boots the 2nd stage u-boot from NAND. Then, I can check CONTROL_STATUS. I get 0x01490312. Some of the upper bits are pulled high because our hardware guy set some of the BTMODEs according to this e2e post:
http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/170318.aspx
BTMODE[9:8] = 10 -> Setup for RGMII Ethernet PHY mode
BTMODE[7] = 1 -> Disable Internal delay
And he also set:
BTMODE[14:13] = 10 -> CS0MUX set for a/a/d muxed device
But that post is actually for an EMAC boot, and TRM says that for NAND, CS0MUX must be 0. So I the above pull-ups to pull-downs, to try to match the DM814x EVM; then CONTROL_STATUS was 0x00010312. But that did not work either, and now I get "ECC: uncorrectable" errors on that board when the 2nd stage is loaded.
I checked the GPMC_WAIT0 line - it pulses during the access, but it is not stuck low.
So, I'm wondering:
- Could the ROM code have a problem with 128 byte oobsize vs 224 byte spare?
- Could the ROM code in DM814x have a different Supported NAND Device table than what is in TRM?
- Is there any way to know why the ROM code rejected the NAND boot?
- Any other ideas?
Thanks,
Dan -