Hello,
I am using the ADC128S102WGMPR in a design in which the power is applied (5V) to the ADC prior to the FPGA which ultimately controls the SPI bus. Between the FPGA and converter is a high-speed opto-coupler and an inverter/buffer which also happens to be powered up before the FPGA. I am following the suggested circuit which ramps the voltage to VA faster than VD. The 5V that powers the inverter/buffer will also ramp up at the same rate as VA.
When power is applied to the FPGA, the CSbar remains low (continuous read) and the CLK and MOSI begin to transmit to the ADC. When doing this, the ADC digital output (MISO) seems to be random even though the analog inputs and digital inputs are stable.
If I force the FPGA to power up before the ADC then the MISO matches the analog inputs. Is there a problem with powering up the ADC with CSbar and CLK low and never toggling the CSbar line prior to sending the CLK and MOSI signals?
Thanks,
Bill