Hi,
I have implemented a circuit similar to shown in http://www.ti.com/lit/an/snla122/snla122.pdf Figure1. I apply an 8-bit counter, which is 8B/10B encoded to the LMH0340. At the recevier side, I decode the parallel output of the LMH0341 via 8B/10B decoder again. However, I have to apply several RESETs to see that the correct data pattern on the FPGA. The number of RESETs is totally random. I have also tried applying only 0xBC (K28.5) caharacters continuously, and I saw the same result. The data alignment seems to depend on RESET timing. Could you please tell me a deterministic way to synchronize data correctly at the LMH0341 side?
Thanks & Regards,
Nizam AYYILDIZ