Hi ALL,
I am sorry to trouble you.
And I have a problem that need your help.
The MCU I work is LX4F230H5QR.
The SSI is configured as SPI and work in slave mode and configured as SSI_FRF_MOTO_MODE_0 .
But when I finished sending data to SSI TX FIFO, I can still see the data on the TX port with oscilloscope.
Below is my code, Please take a look and tell me if there is any problem.
I send 0x1122 to SSI TX FIFO every 200ms for 30 times.
But after sending finished, I can still measure the data ( never ending) on the TX port with oscilloscope.
This is really emergency, you are so appreciated to help me with this.
Thanks in advance.
#include "include/spitofpga.h"
#include "include/datatype.h"
#include "driverlib/timer.h"
#include "driverlib/rom.h"
#include "driverlib/timer.h"
unsigned short datafpga[512];
unsigned long datalengthspi;
unsigned short datathislength;
unsigned short uaspi[2]={0x1122,0x2233};
//*****************************************************************************
//
// SSIO Port Function Inits
//
//*****************************************************************************
void
SPIFPGAPortFunctionInit(void)
{
//
// Enable Peripheral Clocks
//
SysCtlPeripheralEnable(SPI_FPGA_SSI1_PERIPH);
SysCtlPeripheralEnable(SPI_FPGA_GPIO_PERIPH);
//
// Enable SSI1 SSI0TX
//
GPIOPinConfigure(SPI_FPGA_SSITX);
GPIOPinTypeSSI(SPI_FPGA_GPIO_BASE, SPI_FPGA_SSITX_PIN);
//
// Enable SSI1 SSI0FSS
//
GPIOPinConfigure(SPI_FPGA_SSIFSS);
GPIOPinTypeSSI(SPI_FPGA_GPIO_BASE, SPI_FPGA_SSIFSS_PIN);
//
// Enable SSI1 SSI0CLK
//
GPIOPinConfigure(SPI_FPGA_SSICLK);
GPIOPinTypeSSI(SPI_FPGA_GPIO_BASE, SPI_FPGA_SSICLK_PIN);
//
// Enable port PF0 for SSI1 SSI1RX
// First open the lock and select the bits we want to modify in the GPIO commit register.
//
HWREG(SPI_FPGA_GPIO_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY_DD;
HWREG(SPI_FPGA_GPIO_BASE + GPIO_O_CR) = 0x1;
//
// Enable SSI1 SSI0RX
//
GPIOPinConfigure(SPI_FPGA_SSIRX);
GPIOPinTypeSSI(SPI_FPGA_GPIO_BASE, SPI_FPGA_SSIRX_PIN);
}
//*****************************************************************************
// Init Timer4 for sending data to SSI1 every 200ms
void
TimerSendStatusTOFPGA(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER4);
TimerConfigure(TIMER4_BASE, TIMER_CFG_PERIODIC);
TimerLoadSet(TIMER4_BASE, TIMER_A, 16000000);
// Setup the interrupts for the timer timeouts.
IntPrioritySet(INT_TIMER4A, 4 << 5);
IntEnable(INT_TIMER4A);
TimerIntEnable(TIMER4_BASE, TIMER_TIMA_TIMEOUT);
TimerEnable(TIMER4_BASE, TIMER_A);
}
//*****************************************************************************
//
// Init SPI for Recorder
//
//*****************************************************************************
void
SPIFPGAInit(void)
{
SPIFPGAPortFunctionInit();
SysCtlPeripheralReset(SPI_FPGA_SSI1_PERIPH);
SSIDisable(SPI_FPGA_SSI_BASE);
SSIConfigSetExpClk(SPI_FPGA_SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0,
SSI_MODE_SLAVE, SPI_FPGA_BITRATE, 16);
SSIEnable(SPI_FPGA_SSI_BASE);
TimerSendStatusTOFPGA();
}
//Do nothing but clear interrupt status
void
SSI1IntHandler(void)
{
unsigned long ulStatus;
ulStatus = SSIIntStatus(SPI_FPGA_SSI_BASE, true);
SSIIntClear(SPI_FPGA_SSI_BASE, ulStatus);
}
char aa[50];
short success = 0;
void
Timer4IntHandler(void)
{
TimerIntClear(TIMER4_BASE, TIMER_TIMA_TIMEOUT);
success = SPIFPGASSSendDataptr(uaspi,1);
//TimerDisable(TIMER4_BASE, TIMER_A);
}
//************************************************************************
//
// Test Code, Just for test Usage
// send Data to SPI
//
//************************************************************************
static int timesss = 30;
SPIFPGASSSendDataptr(unsigned short *senddata, short datalength)
{
unsigned long ulData;
if (timesss-- > 0)
{
ulData = (unsigned long)(senddata[0]);
//Just use Uart to send debug message to indicate that transfer data to SSI has finished
memset(aa,0,50);
sprintf(aa,"R:%d\r\n",success);
SendDataToUart((unsigned char *)aa, 50);
return SSIDataPutNonBlocking(SSI1_BASE, ulData);
}
}
Below is the main file
int
main(void)
{
//
// Enable lazy stacking for interrupt handlers. This allows floating-point
// instructions to be used within interrupt handlers, but at the expense of
// extra stack usage.
//
FPULazyStackingEnable();
// Set the clocking to 80MHz.
SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_16MHZ);
SPIFPGAInit();
IntMasterEnable();
while(1)
{
}