I was planning to use the LMK04906 to clean up a SERDES recovered clock from an FPGA to provide a super clean clock that could be used for the FPGA and DACs.
FPGA SERDES - > recovered clock to LMK04906 --> LMK04906 input --> clean clock (back into FPGA and DACs)
The problem is that the FPGA in combo with the LMK04906, I feel like I have three suboptimal choices to provide a clock to clean for the LMK04906:
a)dedicated clock output that is psuedo-differential ( so I couldn't do LVDS, but I could provide a pseudo differential 2.5V signal to the LMK04906)
b)dedicated clock output that is single ended to the LMK04906
c)regular I/O output that is true differential and could do LVDS/LVPECL (downfall of this is that I would have increased jitter on these pins output because it is not a dedicated PLL clk output.
Therefore, I was interested in what the best solution would be for the input to the LMK04906
Thanks