Dear sir,
We are using your DM8107 Processor in one of our new product.
While going through PCB design guidelines of" SPRS813_DM8107_11-21-12_Datasheet.pdf" and referring your demo board PCB, it is observed that in DDR3, DDR CLK differential signal having trace width 3.91 mils with air gap (separation between differential traces) 5.91 mils for 4 layer board stack up.
In this regard, pl refer your Table 8-60 (PCB Stack up specification) under heading "8.13.3.5 PCB Stack UP".
1. In order to obtain specified impedance (50 ohm for single ended and 100 ohm for differential ) , we would like to know, what stack up details ( substrate, trace width, gap.. and other details) did you follow for 4Layer and 6 layer board?.
2. How many layers do you specifically recommend and why ?
3. We would like to go for higher layers provided it fetches us with valuable gain.
It would help us in progressing further.
Regards,
Ashok Malhotra
Hoping for quick response,