priority levels in MSMC arbitration

hi,

I have a question with MSMC of C6657.

I plan that 2 cores share the same memory area in MSM. Core1 could access these memories anytime with highest priority than other masters. And Core0 could not access these memories when Core1 is accessing.

So I found ‘MSMC Bandwidth Management in MSMC user guide below’,  But I still wonder what the priority level point to.

The arbitration scheme attempts to allocate accesses fairly to requestors at the same
priority level. However, it is not sufficient to ensure a bound on the wait times
experienced by lower priority requests. Consequently, requestors could be starved for
access when there is heavy traffic at higher priority levels. To avoid indefinite starvation
for lower priority requests, the MSMC features a bandwidth management scheme that
limits starvation times.

Does the priority level mean the priorities of BUS Masters (corpac0, corpac1, EDMA3, etc) which could be configured by chip level registers?

If not, could you let me know what the priority level mean in MSMC and how to configure it such as the above?

Thank you in advance.

bai