Part Number:TPS2662
Hi,
We are planning to introduce TPS26625 onto one of our products. For this, we need the latest status on the UL 2367 recognition.
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TPS2662: Updated status of UL recognition
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EV2300: Can the EV2300 I2C link works in multi-master mode?
Part Number:EV2300
Hello,
I am developing a SW for a MCU controller interfaced to a BQ28Z610 by the I2C link.
For debug purposes, sometime I need to read the BQ parameters while the MCU is working accessing the I2C, too.
I use the bqStudio and EV2300 to read status and parameters.
I have noticed about frequent misreading of the data by the MCU: may those misreading be due the EV2300 which conflicts the I2C bus?
In case, are there some configuration in EV2300 or bqStudio for multi-master, or do I have to add misreading traps in the code of the MCU?
Thanks for reply.
Maurizio
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TS5A21366: Can I tie IN1 & IN2 together with single control signal along with other control circuit?
Part Number:TS5A21366
Hi TI experts,
For current project I'm evaluating using TS5A21366 to isolate the ADC signal from potentiometer to uController.
However I want to know if I can use only one control signal for IN1 & IN2.
Is this possible or is there any internal circuitry that I need to pay attention to?
Externally there is a pull down resistor 10K on the control signal for another PowerFET circuitry control.
Basically I wanted to use single signal to toggle the MOSFET and TS5A21366 if possible.
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CCS/PROCESSOR-SDK-AM65X: The mmap of R5F
Part Number:PROCESSOR-SDK-AM65X
Tool/software: Code Composer Studio
Hello,
I am trying to speed up my R5F program by executing it in the fastest memory which is TCM I supposed.
And I have some questions about the mmap of R5F:
- I learned that the start address of TCMB is 0x40000000 from "Table 2-6. MCU_ARMSS Memory Map" in the TRM; however, from the memory layout in linker_r5.lds, the start address of TCMB is 0x41010000 which is not matched with the value in TRM.
- What OCMRAM and MSMC3 are? It seems that TRM does not mention these memories.
MEMORY
{
VECTORS (X) : origin=0x41C7F000 length=0x1000
/* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
RESET_VECTORS (X) : origin=0x41C00000 length=0x100
/* MCU0_R5F_0 local view */
MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
/* MCU0_R5F_1 SoC view */
MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
/* Fully avaialble for apps. Used by SBL to load SYSFW */
OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
/* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
/* MCU0 share locations */
OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
/* AM65XX M4 locations */
MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
/* Reserved for DMSC */
MSMC3_DMSC (RWIX) : origin=0x700F0000 length=0x10000 /* 64K */
MSMC3_H (RWIX) : origin=0x70100000 length=0xF2000 /* 1MB -56K */
MSMC3_NOCACHE (RWIX) : origin=0x701F2000 length=0xE000 /* 56K */
DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
/* Additional memory settings */
} /* end of MEMORY */Regards,
Hungwei
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BQ25895: BQ25895 application
Part Number:BQ25895
customer use BQ25895
1. It will appear restart or shutdown while BQ25895 lost the power supply suddenly on the boost mode？it will trans to battery supply automatically？or needs to soft switch？
2.If not connet usb com，BQ25895 can work normally？cpu usb work for otg funtion
3. BQ25895 has the temp detect funiton，but how it detect the battery temp？or only detect BQ25895 temp itself？
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TDA2EVM5777: linux openvx usecase performs badly
Part Number:TDA2EVM5777
Hi
I have transplanted Alg_OpenVx in "\vision_sdk\apps\src\rtos\alg_plugins\openvx" on A15 core running linux.
A usecase was developed to test. The chains are as follow:Capture -> Alg_OpenVx (A15)-> Display_M4 (IPU1_0).
The parameters of vxHarrisCornersNode remain unchanged.But the result is not consistent with the usecase in rtos。
In addition, the usecase is still drawing corners when i pause it by pressing ctrl+z.
Could you please give me hand to solve the problems?
Regards
(Please visit the site to view this video)
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CCS/BQ24195L: Sample Code
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DS90UB947-Q1: does 947 support only D0-D3 data?
Part Number:DS90UB947-Q1
hello
does 947 support only D0-D3 data without D4-D7 data?
ISP IC is T7 from the manufacturer of allwinner in China.
Thanks
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TMS320F28377D: Flash modified unexpectedly after power cycle
Part Number:TMS320F28377D
Hi team,
I noticed a rare issue in my customer's project. Currently they are using F28377D with a customized bootloader. In the bootloader, they have a CRC algorithm as below. Under normal conditions, the code was able to pass the CRC test successfully. And the code is widely used in all their products. So we believe the CRC algorithm it self is right.
However, we noticed that if the MCU is powered down(together with power stage), there is a possibility that the code cannot pass the CRC test after the next power up. It seems that the Flash is modified during the power down. We believe that should be some unexpected spikes or interference which caused this problem.
Could you please give some instructions on which may cause the Flash modification problem？ The hardware design around which pin should be checked carefully?
{
UINT16 uiCRC = 0, uiNonZeroDetect = 0, temp,i;
UINT8 z;
UINT16* p;
UINT16 crc_table[256];
for(i=0;i<=255;i++)
{
z = i ^ (i >> 1);
z = z ^ (z >> 2);
z = z ^ (z >> 4);
*(crc_table + i) = z & 1 ? 0xC001 : 0;
*(crc_table + i) ^= i << 6 ^ i << 7;
}
p = (UINT16 *)APP_START_ADDR;
for (;(UINT32)p<=APP_END_ADDR;p++)
{
temp = *p;
uiNonZeroDetect |= temp;
uiCRC = (uiCRC >> 8) ^ *(crc_table + ((uiCRC ^ (temp >> 8))& 0x00ff));
uiCRC = (uiCRC >> 8) ^ *(crc_table + ((uiCRC ^ temp )& 0x00ff));
}
if ((uiCRC == 0) && uiNonZeroDetect)
{
return(1);
}
return(0);
}
Regards,
Brian
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CCS/TMS320F28377D: A question about CCS Version: 8.3.0.00009 compile problem
Part Number:TMS320F28377D
Tool/software: Code Composer Studio
Hi.
Question1: In the following figure, I set a breakpoint at line 388, The actual breakpoint appears at line 390,
When you go to the next step, The breakpoint appears at line 393, And go into execution.
How do I get the software to execute line 388?
Thank you for your reply.
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BQ24715: BQ24715 cutoff cuurent setting
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CCS/TMDSLCDK138: TMDSLCDK138 CAN NOT CONNECT WITH JTAG
Part Number:TMDSLCDK138
Tool/software: Code Composer Studio
Hi,
I want to use ccsv5 and XDS100V2 emulator to debug my TMDSLCDK138,but it does not work.
I have another board with omapl138, it can debug well with XDS100V2.
Checked the hardware between the emulator and TMDSLCDK138 connection without problem
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length failed.
The JTAG IR instruction scan-path is stuck-at-ones.
The test for the JTAG DR bypass path-length failed.
The JTAG DR bypass scan-path is stuck-at-ones.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 1: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 2: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 3: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 4: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 5: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 6: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
Test 2 Word 7: scanned out 0x00000000 and scanned in 0xFFFFFFFF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.
The JTAG IR Integrity scan-test has failed.
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BQ40Z50-R2: BQ40Z50-R2 Current and Voltage setting
Part Number:BQ40Z50-R2
Dear,
For BQ40Z50, we use it in battery pack, usually the charge current and charge voltage is set, we want to know at what conditions, the charger current or charge voltage will be set to 0?
Thanks.
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TPS65094: DRVL and PGNDSNS route when FET is far from PMIC
Part Number:TPS65094
Dear Sir,
I found PGNDSNS is sensitive signal and DRVL is aggressive signal in Layout Checklist.
In intel's design 560683-apl-rvp-crb-lpddr3-ti-tdk-rev2p0, DRVL is parallel to PGNDSNS,is it wrong?
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AM3352: security error (Error -241 @ 0x0) found on AM3352
Part Number:AM3352
Hi, we found an error on our AM3352 with JTAG XDS100 V3.0,following is the messages we got:
Error connecting to the target:
(Error -241 @ 0x0)
A router subpath could not be accessed.
A security error has probably occurred.
Make sure your device is unlocked.
(Emulation package 8.0.903.6)
we can pass test connection with the same tools setting. here are messages from testig procedure
Start: Texas Instruments XDS100v3 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\Users\bitla\AppData\Local\TEXASI~1\CCS\
ti\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusbv3.dll'.
The library build date was 'Jan 24 2019'.
The library build time was '14:27:46'.
The library package version is '8.0.903.6'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 64 - 01 00 500.0kHz O good value measure path length
2 64 + 00 00 1.000MHz [O] good value apply explicit tclk
There is no hardware for measuring the JTAG TCLK frequency.
In the scan-path tests:
The test length
Is there any tips about how to fix this iusse?
Thanks
Hugo
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LM5060-Q1: LM5060-Q1
Part Number:LM5060-Q1
(Please visit the site to view this file)Attached detailed failure analysis report
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DS100BR111: DS100BR111 can support standard interface
Part Number:DS100BR111
Hi Guys
Can our DS100BR111 device support SGMII redriver? How determine which type of protocol interface we can support?
I just see the SGMII 1.25Gbps and only need two I/O port(RX and TX); Our device also has two pair differential ports（RX and TX）10Gbps. So I think it can support this. But not sure whether it is correct by using this parameters.
Your feedback are very appreciated.
Thanks
-Pengfei
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Linux/LINUXSDK-OMAPL138: Dynamic Voltage and Frequency Scaling (DVFS) on OmapL138
Part Number:LINUXSDK-OMAPL138
Tool/software: Linux
Hi,
We have a custom board build using the OMAPl138. The device is running Kernel version 3.10.12. We are working on implementing the power save governor in the DVFS on custom OMAPl138. Our plan is to have our device use the least frequency when device is not being used.
The following governors were available in CPUFreq frame work in our system by default.
- Performance.
- Ondemand
- Userspace
The available scaling frequencies in our system are
/sys/devices/system/cpu/cpu0/cpufreq # cat scaling_available_frequencies
300000 200000 96000
cat scaling_cur_freq
300000
Have included the powersave governor as part of our kernel and post that we observe the powersave governor entry in the list of CPUFreq framework.
Am able to set the governor as scaling governor but i,m not able to change the frequency for the governor and i,m seeing below error. Request to share your comments on this asap.
cat scaling_governor
powersave
/sys/devices/system/cpu/cpu0/cpufreq # echo 96000 > scaling_cur_freq
-sh: can't create scaling_cur_freq: Permission denied
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TPS544B20: Schematic Review
Part Number:TPS544B20
Dear Team,
We are using the below parts in our design.
1) TPS544B20RVFT- 12V to 5V regulator
2) TPS54526PWP- 12V to 1.15V and 12V to 3.3V(Please visit the site to view this file)
Attached here with the schematics of the above two parts
Kindly review and let us know on the review comments
Thanks and Regards
Vishak N
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TMS320F280049: Motor SDK pkan for F28004x series
Part Number:TMS320F280049
Hi,
Has TI finalized the date on release of Motor SDK for F28004x controllers? I am waiting for it and I would like to know if there is a possibility to get the beta version.
Also, will the code structure in Motor SDK be similar to Motorware?
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