Part Number:DRV5032

Hello,

Can you please direct me to the Magnetic field calculator on TI website?

Thank you.

Part Number:MSP430G2553

I've found several threads on various sites relating to this idea.  There would be a permanent bootloader that on a button push would look for a firmware update file on a microSD card, and if found, flash the contents of the file to the application portion of memory.  But I haven't found a completed working example of such a bootloader.  Does anyone know of one?  Preferably in assembler.

I found a port of the PFatFs library for Energia, and the demonstration .ino compiled ok, but was over 6K and used up most of ram.  Since I would need only limited read-only FAT functionality, perhaps there might be a simpler FAT library I could use, but research indicates that supporting a file system just needs lots of code, so maybe PFatFs is as good as it gets.

Anyway, I would appreciate any ideas and suggestions.

Part Number:LM5121-Q1

Vin is 27 to 55

Vout is Vin to 65

Lin is 4.1uH

Rosc is 43K or running about 208Khz

Cout is 10,000uF

Inrush limiting works fine, safely charging Cout to Vin, However Boost operation above Vin does not work.

One pulse on LO pin,  and chip resets itself and cycles itself continuously at SS or RES rate. Cout never charges above Vin.

Schematic follows:

Part Number:TMS320F28377S

Tool/software: Code Composer Studio

To try and simplify this, I have a LaunchpadXL with the TMS320F28377S and CCS v8.2 connected to it running blinky_cpu01. I'm trying to move the boot pins to GPIO70 so that I can pull GPIO70 high and get a blinking LED  on powerup instead of using GPIO72 & GPIO84.  If there's a simpler way of doing this, let me know. With that in mind:

1) How do I configure EMU_BOOTCTRL and test this change? I cannot find any sample code for doing this. The only reference anywhere to the memory address is 6.9.1 of the datasheet.

2) How do I test that change? I found on google something about issuing a "debug restart", but this new version of CCS has "CPU Reset" and "Restart" in the toolbar. Am I supposed to pause the debugger, click "CPU Reset" then hit "Resume (F8)" to check that the light will blink only if GPIO70 is pulled high?

3) Once I settle on EMU_BOOTCTRL settings, how do I then write the BOOTCTRL register? What memory address is it? Are there multiple BOOTCTRL registers for multiple zones I need to set? Do I need to use the Flash_API library and write a program that uses that? I saw some references to an old Flash-editor plugin for CCS on this forum that can apparently do the job - does that still exist somewhere? Someone else here modified the codestart.asm file to do it, is that what I'm supposed to do?

4) I want to assign GPIO70 for both boot pins, and if that pin is high, it boots into flash, and if it's low, it won't run the code and you need to plug a debugger in to run the code from CCS. So am I correct in understanding that EMU_BOOTCTRL and BOOTCTRL should be written to 0x46460B5A?

Thanks,

David

Part Number:SN74LVC8T245-EP

Hi,

For level shifting certain logic from LVTTL (3.3V) to TTL (5V) logic I have incorporated SN74LVC8T245MDWREP and CALVC164245MDGGREP for Octal and 16 bit data level translation.

Are the devices SN74LVC8T245MDWREP and CALVC164245MDGGREP  capable to level shift signals upto 64 MHz? What is the higher limit of frequency for the signal through the level translators?

Can the signal of 5V be transmitted through 10 inch (upto) traces running over backplane from the cards having these level shifters?

Further I am looking for IBIS models for SI simulation for the below listed components.

Item Manufacturer Part Number
1 CALVC164245MDGGREP
2 CD74HCT423M
3 TLC555MJGB (5962-8950301PA)/SE555CJG/TLC555MJG
4 TPS73601MDCQREP
5 DRV8873HPWPRQ1
6 SN74HC253QDREP
7 SN74LVC8T245MDWREP (text format data available on TI website)

Thanks and Regards,

Subramaniam

Part Number:AM3358

Tool/software: Linux

I am able to successfully build and deploy an arago-base-image onto an SD card, but when I look in the build directory I cannot find a populated sysroots directory for my target.  I have used Yocto builds for other processors in the past and have leveraged the sysroots directory for projects.  Is a populated sysroots directory located elsewhere, or is there an option to the build I must enable/disable to populate it?

Part Number:TMS320F28379D

Hi, I am unsure as to which GPIO pins do the 8 Xbar outputs connect to. The ePWM Xbar outputs seem straightforward, they would connect to respective number ePWM module, correct? But it is not clear what the Xbar outputs connect to. For example, what GPIO pin does the XBAR3 output connect to?

Part Number:AM5728

Tool/software: TI-RTOS

I am trying to run the NIMU Basic Example for M4 on ethernet port 1 on our custom board. By default, the app runs on ethernet port 0. I want to run it on port 1 because port 0 on our custom board is not currently functional due to a hardware issue. I have tried many different ways to get the app to use port 1 instead of port 0, but all have been unsuccessful. If someone could explain to me how to correctly go about this, that would be greatly appreciated. It is also important to note that this example must run on the M4 (i.e. I can't use the dual MAC example that runs on the ARM) because we currently cannot boot into the A15.

Part Number:TPS92691-Q1

Team,

The data sheet recommend's 6.5V as the minimum continuous input voltage with crank support down to 4.5V? If i am trying to operate down to 6V continuos what are the conditions that need to be considered? Is it that i have to apply greater than 6.5V and than i can go down to 6V. Does the IC required greater than 6.5V at startup or can i start up with an input of 6V? 

Part Number:TPS65987D

Hi Team,

Please help to confirm the difference between TPS65987DDJRSHR and TPS65987DDHRSHR

Thanks

Part Number:TMS320F28379D

In the example cmpss_asynch, the function GPIO_SetupPinMux is used to set the pin to XBAR 3. Does this function essentially access the GPAMUX1 and GPAGMUX1 registers and sets the required bits?

Also, I notice that this setup is done in the main function, rather than in the initialization functions. Why is that?

Part Number:CC2652R

Team,

Is it possible to use a single ended output MEMS oscillator to replace the crystal on the device?

Part Number:TIDA-01480

Team, 

I can't seem to be able to locate a power reference design for Xilinx Zynq Ultrascae+ FPGA - XZU7EV. 

Do we have one? 

Thanks

Viktorija

Part Number:TMS320F28069M

Tool/software: TI C/C++ Compiler

I have been working on a project that is based on the InstaSPIN projects which uses the method for putting the ISR into RAM which looks like:

#pragma CODE_SECTION(somefxn, "ramfuncs")

// Copy fxns from flash to ram at startup
mem_copy(....)

and I'm trying to move away from that to the more straight-forward approach that is talked about here: http://processors.wiki.ti.com/index.php/Placing_functions_in_RAM . I can see in my .map file, that the functions are placed in the right place, also when I run the code and use a breakpoint in the debugger, I see that my ISR is being run, and the program counter shows the right address, but for some reason a lot of things suddenly start breaking. My eQEP module stops counting, I no longer get interrupts on my SCI interface(which is being run from flash) and I can't send information out of the SCI, I use a blocking write call and it happily allows me to write to the Tx buffer but nothing ever comes out the other end. Any ideas on what's going on here?

Part Number:BQ27421-G1

Hi - I am planning to get a BQ27421-G1 EVM for testing, and I have two battery types for testing - 4.2V and 4.3V LiPo. It seems the EVMs are sold by chemistry type (A and B for 4.2, 4.3 resp). Can this be changed to test different battery types with a single EVM? 

Part Number:LM5175

(Please visit the site to view this file)Hi,

Attached schematics buck-boost converter used to convert input voltage 6-24V to output 12V, 3 amp. This power supply serviced for CPU module with miniPCI added card. And now I faced problem that one type of PCIe added card is doesn't work. After careful investigation I understood that switching noise of the PS affect to PCIe functionality. My question is what is the way to reduce this switching noise of the PS

Thank you

Berlin Stanislav

Part Number:INA223

Hi Team,

Please kindly help to confirm the Vout calculation and sch.

Our setting as below pic.

And the calculation as below:

Rsense=0.001 Ohm , current at 278W/12V=23.167A
Vsense=1m Ohm x 23.167A = 0.023167V
INA223 Vout =(DC IN) *(Vsense)*(POWERgain)
INA223 Vout =12V*0.023167*10=2.78004V

Given INA223 Vout from above we must divide the voltage down to meet the IMVP8 Psys full scale input voltage of 2V
R0704=1.96K and R0706=4.99K gives a full scale Psys voltage of 2V.

Thanks

Part Number:LAUNCHXL-F28379D

Hi,

I am currently using IMU9250 to get readings for Pitch via UAR with LaunchXL-F28379D. The output from this IMU is as follows:

<-8.24>

<-17.44> and so on..

I am able to get the output with basic sci loopback code. However, I want to use interrupts, as I need to call SCI within another protocol.

When I use the following code, I get no proper output but gibberish values.

What am I missing here?

//###########################################################################
//
// FILE:   Example_2837xDSci_FFDLB_int.c
//
// TITLE:  SCI Digital Loop Back with Interrupts.
//
//! \addtogroup cpu01_example_list
//! <h1>SCI Digital Loop Back with Interrupts (sci_loopback_interrupts)</h1>
//!
//!  This program uses the internal loop back test mode of the peripheral.
//!  Other then boot mode pin configuration, no other hardware configuration
//!  is required. Both interrupts and the SCI FIFOs are used.
//!
//!  A stream of data is sent and then compared to the received stream.
//!  The SCI-A sent data looks like this: \n
//!  00 01 \n
//!  01 02 \n
//!  02 03 \n
//!  .... \n
//!  FE FF \n
//!  FF 00 \n
//!  etc.. \n
//!  The pattern is repeated forever.
//!
//!  \b Watch \b Variables \n
//!  - \b sdataA - Data being sent
//!  - \b rdataA - Data received
//!  - \b rdata_pointA - Keep track of where we are in the data stream.
//!    This is used to check the incoming data
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.05.00.00 $
// $Release Date: Thu Oct 18 15:48:42 CDT 2018 $
// $Copyright:
// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Defines
//
//
// Globals
//
Uint16 sdataA[2];    // Send data for SCI-A
Uint16 rdataA[2];    // Received data for SCI-A
Uint16 rdata_pointA; // Used for checking the received data

//
// Function Prototypes
//
interrupt void sciaTxFifoIsr(void);
interrupt void sciaRxFifoIsr(void);
void scia_fifo_init(void);
void error(void);
void scia_xmit(int a);
void scia_msg(Uint16 *msg);

//
// Main
//
void main(void)
{
   Uint16 i;
   Uint16 ReceivedChar;
   Uint16 *msg;
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
   InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
   InitGpio();

//
// For this example, only init the pins for the SCI-A port.
//  GPIO_SetupPinMux() - Sets the GPxMUX1/2 and GPyMUX1/2 register bits
//  GPIO_SetupPinOptions() - Sets the direction and configuration of the GPIOS
// These functions are found in the F2837xD_Gpio.c file.
//
   //
      GPIO_SetupPinMux(43, GPIO_MUX_CPU1,15);
      GPIO_SetupPinOptions(43, GPIO_INPUT, GPIO_PUSHPULL);
      GPIO_SetupPinMux(42, GPIO_MUX_CPU1,15);
      GPIO_SetupPinOptions(42, GPIO_OUTPUT, GPIO_ASYNC);
      GPIO_SetupPinMux(19, GPIO_MUX_CPU1, 2);
      GPIO_SetupPinOptions(19, GPIO_INPUT, GPIO_PUSHPULL);
      GPIO_SetupPinMux(18, GPIO_MUX_CPU1, 2);
      GPIO_SetupPinOptions(18, GPIO_OUTPUT, GPIO_ASYNC);
   //

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
   DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
   InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
   IER = 0x0000;
   IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
   InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
   EALLOW;  // This is needed to write to EALLOW protected registers
   PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr;
  // PieVectTable.SCIA_TX_INT = &sciaTxFifoIsr;
   EDIS;    // This is needed to disable write to EALLOW protected registers

//
// Step 4. Initialize the Device Peripherals:
//
   scia_fifo_init();  // Init SCI-A

//
// Step 5. User specific code, enable interrupts:
//
// Init send data.  After each transmission this data
// will be updated for the next transmission
//
   *msg =(char)ScibRegs.SCIRXBUF.all;
   scia_msg(msg);


//
// Enable interrupts required for this example
//
   PieCtrlRegs.PIECTRL.bit.ENPIE = 1;   // Enable the PIE block
   PieCtrlRegs.PIEIER9.bit.INTx1 = 1;   // PIE Group 9, INT1
   PieCtrlRegs.PIEIER9.bit.INTx2 = 1;   // PIE Group 9, INT2
   IER = 0x100;                         // Enable CPU INT
   EINT;
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
//    for(;;);
}

//
// error - Function to halt debugger on error
//
void error(void)
{
    asm("     ESTOP0"); // Test failed!! Stop!
    for (;;);
}

//
// scia_xmit - Transmit a character from the SCI
//
void scia_xmit(int a)
{
    while (SciaRegs.SCIFFTX.bit.TXFFST != 0) {}
    SciaRegs.SCITXBUF.all =a;
}

//
// scia_msg - Transmit message via SCIA
//
void scia_msg(Uint16 * msg)
{
    int i;
    i = 0;
    while(msg[i] != '\n')
    {
        scia_xmit(msg[i]);
        i++;
    }
}

//
// sciaTxFifoIsr - SCIA Transmit FIFO ISR
//
/*interrupt void sciaTxFifoIsr(void)
{
    Uint16 i;

    for(i=0; i< 2; i++)
    {
       SciaRegs.SCITXBUF.all=sdataA[i];  // Send data
    }
    SciaRegs.SCIFFTX.bit.TXFFINTCLR=1;   // Clear SCI Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ACK
}*/

//
// sciaRxFifoIsr - SCIA Receive FIFO ISR
//
interrupt void sciaRxFifoIsr(void)
{
    Uint16 i;
    i=SciaRegs.SCIRXBUF.all;  // Read data
    scia_xmit(i);
    SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;   // Clear Overflow flag
    SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;   // Clear Interrupt flag
    PieCtrlRegs.PIEACK.all|=0x100;       // Issue PIE ack
}

//
// scia_fifo_init - Configure SCIA FIFO
//
void scia_fifo_init()
{
   SciaRegs.SCICCR.all = 0x0007;      // 1 stop bit,  No loopback
                                      // No parity,8 char bits,
                                      // async mode, idle-line protocol
   SciaRegs.SCICTL1.all = 0x0003;     // enable TX, RX, internal SCICLK,
                                      // Disable RX ERR, SLEEP, TXWAKE
   SciaRegs.SCICTL2.bit.TXINTENA = 1;
   SciaRegs.SCICTL2.bit.RXBKINTENA = 1;
   SciaRegs.SCIHBAUD.all =0x00;  // 9600 baud @LSPCLK = 50MHz
                                   //(200 MHz SYSCLK).
   SciaRegs.SCILBAUD.all =0x0F;
   //SciaRegs.SCICCR.bit.LOOPBKENA = 1; // Enable loop back
   SciaRegs.SCIFFTX.all = 0xC022;
   SciaRegs.SCIFFRX.all = 0x0022;
   SciaRegs.SCIFFCT.all = 0x00;

   SciaRegs.SCICTL1.all = 0x0023;     // Relinquish SCI from Reset
   SciaRegs.SCIFFTX.bit.TXFIFORESET = 1;
   SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;

   ScibRegs.SCICCR.all = 0x0007;   // 1 stop bit,  No loopback
                                   // No parity,8 char bits,
                                   // async mode, idle-line protocol
   ScibRegs.SCICTL1.all = 0x0003;  // enable TX, RX, internal SCICLK,
                                   // Disable RX ERR, SLEEP, TXWAKE
   ScibRegs.SCICTL2.all = 0x0003;
   ScibRegs.SCICTL2.bit.TXINTENA = 1;
   ScibRegs.SCICTL2.bit.RXBKINTENA = 1;
   ScibRegs.SCIHBAUD.all = 0x00;
   ScibRegs.SCILBAUD.all = 0x0F;
   ScibRegs.SCICTL1.all = 0x0023;  // Relinquish SCI from Reset
   ScibRegs.SCIFFTX.all = 0xE040;
   ScibRegs.SCIFFRX.all = 0x2044;
   ScibRegs.SCIFFCT.all = 0x0;
}

//
// End of file
//

Part Number:DRV8343-Q1

Hi team,

I have some question about gate resister.

1. Can DRV8343 also drive FETs in parallel?

2. Does DRV8343 need gate resisters when driving FETs in parallel?

3. If gate resister is required, how should the gate resister be determined?

(Is it needed to consider the balance with the setting value of gate current etc.)

4. Will adding the gate resister affect the FET gate state monitoring function etc. of the IC?

Best regards,

Tomoaki Yoshida

Part Number:TMS320F28379D

Tool/software: Code Composer Studio

I am using the sd card example code to learn the FATFS library. I am trying to make a file and write some data to it. The file contents are empty. Please find below the code :

    FRESULT fresult;
    FIL fil;
    char line[] = "Hello World";   

fresult = f_mount(0, &g_sFatFs);
    if(fresult != FR_OK)
    {
        UARTprintf("f_mount error: %s\n", StringFromFresult(fresult));
        return(1);
    }


    WORD bw =0;
    fresult = f_open(&fil, "message2.txt",FA_WRITE | FA_OPEN_EXISTING);
    fresult = f_write(&fil, line, (WORD)strlen(line), (void *)&bw);
    f_sync(&fil);
    f_close(&fil);

I am not getting any error in any of the steps.