Part Number:DRV8301

Hello,

I recently downloaded the Universal GUI for instaSPIN. Before installing, it asked me whether I wanted to Uninstall the previous version of the GUI (bought this kit about 4 years ago - finally using it), and I answered "yes". The installation got hung up, so I eventually hit the "Cancel" button. Tried running it anyway and saw a really ugly GUI. So, I figured I'd re-install it, but to save some time I'd run the uninstallers in the gui composer folder. They are 'uninstall_ti_dspack.exe' and 'uninstall_ti_emupack_5.1.641.0.exe'. I reinstalled the Universal GUI program (successfully this time), but I still have the ugly GUI. The following messages appear on the Configuration page:

Restarting Program Model...
Initializing target : C:\ti\guicomposer\eclipse\workspace\.metadata\.plugins\com.ti.binding.program\appConfig.ccxml
Loading program: null
sun.org.mozilla.javascript.internal.WrappedException: Wrapped java.lang.NullPointerException (<Unknown source>#18) in <Unknown source> at line number 18Restart Completed.

I've attached a Screenshot of the GUI.

Any ideas what I might need to do to get this running?

Thanks,

Dave Reagan

Part Number:AM5726

Tool/software: Linux

Hi,

We have been developing using the AM5728 IDK dev board and transitioned to bringing a custom board using the AM5726.

It looks like the bootloader is reading an EEPROM for the Board ID.  We did not put an EEPROM on our custom board.  We tried bypassing the Board ID check and forced the 

board to be the AM5728 IDK.  It also looks like it's trying to access the PMIC chip tps65903x chip.  On our custom board, the chip is mapped to I2C2 instead of I2C1.

We are looking into how to remap this in the bootloader.  It also looked like it was trying to load linux from emm1 interface which I think is the eMMC Flash and we want to boot from the SD Card.

We tried forcing the code to boot from mmc0 .

Sample output is below.  Any recommendations or insight into bringing up the board would be appreciated.  

Thanks,

Christine

Output:

could not set LDO1 voltage.
no pinctrl state for default mode
*** Warning - bad CRC, using default environment

reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img

CPU : DRA752-GP ES2.0
Model: TI AM5728BeagleBoard-X15

Board: AM572x IDK REV
DRAM: 2 GiB
OMAP SD/MMC: 0, OMAP SD/MMC: 1
*** Warning - bad CRC, using default environment

tatus=0x116)
Warning: fastboot.board_rev: unknown board revision
GUID Partition Table Header signature is wrong: 0x0 != 0x5452415020494645
part_get_info_efi: *** ERROR: Invalid GPT ***
GUID Partition Table Header signature is wrong: 0x0 != 0x54524150SATA link 0 timeout.
AHCI 0001.030or devices...
Found 0 device(s).
Net: Cou
Hit any key to stop autoboot: 0
i2c_write: error waiting for data ACK (status=0x116)
read error from device: fdf2fa90 register: 0x50!i2c_write: error or waiting for data ACK (status=0x116)
read error from device: fdf2fa90 register: 0x50!i2c_write: error waiting for data ACK (16)
read error from device: fdf2fa90 register: 0x50!Error enabling VMMC supply
i2c_write: error waiting for data ACK (status=0x116)
read error from device: fdf2fa90 register: 0x50!i2c_write: error waiting for data ACK (status=0x116)
read error from dswitch to partitions #0, OK
mmc0(part 0) is current device
i2c_write: error waiting for data ACK (status=0x116)
read error fster: 0x50!Error enabling VMMC supply
Trying to boot Android from eMMC ...
rom device: fdf2fa90 register: 0x50!i2c_write: error waiting for data ACK (status=0x116)
read error from device: fdf2fa90 register: 0x50!Error enabling VMMC supply
mmc - MMC sub system

Usage:
mmc info - display info of the current MMC device
mmc r current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc{on|off}]] - sets user data area attributes
[gp1|gp2|gp3|gp4 cnt [enh] [wrrel {on|off}]] - general purpose partition
nce it is set to complete.
Power cycling is required to initialize partitions after set to complete.
mmc bootbus dev boot_bot part size MB> <RPMB part size MB>
- Change sizes of boot and RPMB partitions of specified device
mmc partconf dev [boot_aeld and 0 / 1 / 2 are the only valid values.
mmc setdsr <value> - set DSR register value

mmc - MMC sub system

Usage:
mmn
mmc part - lists available partition on current mmc device
mmc dev [dev] [part] - show or set current mmc device [partition]
mmc list - lists available devices
mmc hwpartition [args...] - does hardware partitioning
arguments (sizes ih] [wrrel {on|off}]] - general purpose partition
[check|set|complete] - mode, complete set partitioning completed
WARNIof the specified device
mmc bootpart-resize <dev> <boot part size MB> <RPMB part size MB>
- Change sizes of boot and RPMB paRTITION_CONFIG field of the specified device
mmc rst-function dev value
- Change the RST_n_FUNCTION field of theR register value

Wrong Image Format for bootm command
ERROR: can't get kernel image!

Part Number:TMS320F28377S

Tool/software: TI-RTOS

I am running a  SYSBIOS 6.75 project on my TMS320F28377S LaunchXL.

When I run the debugger, the code initially goes straight to reset vector 0x3FE493.

Then, I click on the Pause/Resume and do a CPU reset and restart. This time, the code executes up to main() and the instruction pointer enters the first line of main()

At this point, when I single-step into the main, eventually I land up with the ti_sysbios_family_c28_Hwi_unPluggedInterrupt__I(): being triggered and the console displays:

[C28xx_CPU1] enter main()
ti.sysbios.family.c28.Hwi: line 1032: E_unpluggedInterrupt: Unplugged interrupt flagged: intr# 19
xdc.runtime.Error.raise: terminating execution

I read on previous forum posts that intr#19 indicates an illegal action happened. Please note that at this point in my execution, I am:

-disabling the watchdog (in the main code and it is also disabled in the BIOS config)

-initializing system clock

-initializing GPIO ports and device peripherals.

I pulled the disassembly from the debugger and noticed the Timer Prescale executions before the unPluggedInterrupt() occurs. Is something wrong with the timer settings? I am using the same device clock configurations as in the device.c/.h files for the F28377x family, specific to LaunchPadXL.

Would appreciate some insights on the topic. 

Part Number:CC2640R2F

Hi

I have activated UART logging using the RTSC components and XDC tools from TI.

I am following what was done in this example:

http://processors.wiki.ti.com/index.php/CC26xx_Ouput_TI-RTOS_Log_statements_over_UART#Include_uart_logs.c

I would like to know whether logging exists for the Stack and RTOS and how to activate those logs?

At the moment I only see the logs that I send to the UART.

thanks

Regards

Rui

Part Number:TMS320F28035

I have a board with 2 microcontrollers, one of which is the TMS320F28035. The 2 microcontrollers communicate via SCI. I have to update the TMS320F28035 firmware via the other microcontroller so I should implement the communication protocol with the bootloader on the Piccolo. How can I do?
Thank you

Part Number:TDC7200EVM

Hello,

 I am trying to implement Lidar system with fabricated emitter(LED or laser) and receiver(photodiode).

Because I am not a circuit guy, PCB design is pretty challenging to me; therefore, TIDA-01187 is somewhat hard to me.

So, here are two choices

1. using TDC7200, self-soldering and connecting with Arduino and my fabricated receiver and emitter on a breadboard.

2. using TDC7200EVM, connecting to MSP430, and wiring the SMA connector with my fabricated receiver and emitter on a breadboard.

Which one is more desirable for my project? If any other options extist, please let me know as well. Thank you very much.

Best,

Ted  

Part Number:AM3358

Tool/software: Code Composer Studio

Hi,

I have a custom made board using an AM3358 using DDR2 memory. Booting from SD-card I can see the u-boot-SPL starting up in the terminal. I want to use my J-tag adapter to debug U-Boot and write data to external DDR memory. When I connect to my A8 core in CCS8 I get the message that the core is held in reset.

CCS version: 8.3.0.00009
J-tag adapter: TI-XDS110
OS: Ubuntu 16.04 kernel 4.15.0-46

I was following the course from TI module 6 and module 7:
https://training.ti.com/linux-board-porting-series-module-7-debugging-u-boot-jtag-ccs

I looked at other forums, but the solutions did not work for me. At debug configuration I tried to ONLY select the cortxA8 core.
Do I need a GEL file to trigger the M8 to wake-up the A8 core? I tried the BBB GEL file (which has some DD3 configuration inside instead of DDR2) but that did not work for me.
I wonder if there is an easy way to get this to work now.

Part Number:TMDSICE3359

Tool/software: TI-RTOS

Hello,

I am using CCS v8.3

Processor _sdk_rtos_am335x_5_02_00_10

xdctool 3_51_01_18

Bios_6_76_00_08

pdk_am335x_1_40_01_01       ICEv2.1 eval board

When I copy the example rtos_template_app_am335x into my workspace it automatically selects xdc tools 3.508.24   sysbios 6.73.1.01  older version I have in my TI directory.

I understand that you are making universal API's independent of platform and device but how can I tell if my configuration files are correct.

The rtos seems to run but when I am trying to add any gpio, i2c functionality and I don't see any initialization of I2c or uart.

The bare metal Hello world will print out on the console.

How can I tell if the.... Board_init(boardCfg),   ....peripheralInit() which has i2c init... just jumps over in debug mode cannot step into these functions  If these functions are working?

How can I tell if the platform is correct the only choice in the properties drop down product menu is ti.platforms.evmAM3359 should this be ICE2AM335x which is not a choice.

  I trying to go with the latest documentation Processor SDK RTOS Getting Started Guide. Is there another doc you would recommend?

I've worked before with the Tiva and Concerto with success but progress is slow with this AM335x.

Thank You

Dan

Part Number:TMS320F28379D

Hi E2E team,

I am using EPWM up counting example, I have changed clock division settings and counting only 1 pulse (EPwm1Regs.TBPRD = 1).

In Epwm ISR, I am toggling GPIO25 to verify frequency on the oscilloscope. I am not seeing frequency close to 200 Mhz. I am seeing frequency as 1 MHz.

 My changed code:

//###########################################################################
//
// FILE:   epwm_up_aq_cpu01.c
//
// TITLE:  Action Qualifier Module - Using up count.
//
//! \addtogroup cpu01_example_list
//! <h1> EPWM Action Qualifier (epwm_up_aq)</h1>
//!
//! This example configures ePWM1, ePWM2, ePWM3 to produce an
//! waveform with independent modulation on EPWMxA and
//! EPWMxB.
//!
//! The compare values CMPA and CMPB are modified within the ePWM's ISR.
//!
//! The TB counter is in up count mode for this example.
//!
//! View the EPWM1A/B(PA0_GPIO0 & PA1_GPIO1), EPWM2A/B(PA2_GPIO2 & PA3_GPIO3)
//! and EPWM3A/B(PA4_GPIO4 & PA5_GPIO5) waveforms via an oscilloscope.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v210 $
// $Release Date: Tue Nov  1 14:46:15 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"

//
// Defines
//
#define EPWM1_TIMER_TBPRD  2000  // Period register
#define EPWM1_MAX_CMPA     1950
#define EPWM1_MIN_CMPA       50
#define EPWM1_MAX_CMPB     1950
#define EPWM1_MIN_CMPB       50

#define EPWM2_TIMER_TBPRD  2000  // Period register
#define EPWM2_MAX_CMPA     1950
#define EPWM2_MIN_CMPA       50
#define EPWM2_MAX_CMPB     1950
#define EPWM2_MIN_CMPB       50

#define EPWM3_TIMER_TBPRD  2000  // Period register
#define EPWM3_MAX_CMPA      950
#define EPWM3_MIN_CMPA       50
#define EPWM3_MAX_CMPB     1950
#define EPWM3_MIN_CMPB     1050

#define EPWM_CMP_UP           1
#define EPWM_CMP_DOWN         0

//
// Globals
//
typedef struct
{
    volatile struct EPWM_REGS *EPwmRegHandle;
    Uint16 EPwm_CMPA_Direction;
    Uint16 EPwm_CMPB_Direction;
    Uint16 EPwmTimerIntCount;
    Uint16 EPwmMaxCMPA;
    Uint16 EPwmMinCMPA;
    Uint16 EPwmMaxCMPB;
    Uint16 EPwmMinCMPB;
}EPWM_INFO;

EPWM_INFO epwm1_info;
EPWM_INFO epwm2_info;
EPWM_INFO epwm3_info;

//
//  Function Prototypes
//
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
void update_compare(EPWM_INFO*);

//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
//
//    InitGpio();

//
// Enable PWM1, PWM2 and PWM3
//
    CpuSysRegs.PCLKCR2.bit.EPWM1=1;
    //CpuSysRegs.PCLKCR2.bit.EPWM2=1;
    //CpuSysRegs.PCLKCR2.bit.EPWM3=1;

//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
    InitEPwm1Gpio();
    //InitEPwm2Gpio();
    //InitEPwm3Gpio();

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW; // This is needed to write to EALLOW protected registers
    PieVectTable.EPWM1_INT = &epwm1_isr;
    //PieVectTable.EPWM2_INT = &epwm2_isr;
    //PieVectTable.EPWM3_INT = &epwm3_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

//
// For this example, only initialize the ePWM
//
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    InitEPwm1Example();
    //InitEPwm2Example();
    //InitEPwm3Example();

    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
    EDIS;

//
// Step 4. User specific code, enable interrupts:
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
    IER |= M_INT3;

//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
    PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
    PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
    PieCtrlRegs.PIEIER3.bit.INTx3 = 1;

//
// Enable global Interrupts and higher priority real-time debug events:
//
    EINT;  // Enable Global interrupt INTM
    ERTM;  // Enable Global realtime interrupt DBGM

//
// Step 5. IDLE loop. Just sit and loop forever (optional):
//
    for(;;)
    {
        asm ("  NOP");
    }
}

//
// epwm1_isr - EPWM1 ISR to update compare values
//
__interrupt void epwm1_isr(void)
{
    GpioDataRegs.GPATOGGLE.bit.GPIO25 = 1;
    //
    // Update the CMPA and CMPB values
    //
    update_compare(&epwm1_info);

    //
    // Clear INT flag for this timer
    //
    EPwm1Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;

}

//
// epwm2_isr - EPWM2 ISR to update compare values
//
__interrupt void epwm2_isr(void)
{
    //
    // Update the CMPA and CMPB values
    //
    update_compare(&epwm2_info);

    //
    // Clear INT flag for this timer
    //
    EPwm2Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// epwm3_isr - EPWM3 ISR to update compare values
//
__interrupt void epwm3_isr(void)
{
    //
    // Update the CMPA and CMPB values
    //
    update_compare(&epwm3_info);

    //
    // Clear INT flag for this timer
    //
    EPwm3Regs.ETCLR.bit.INT = 1;

    //
    // Acknowledge this interrupt to receive more interrupts from group 3
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

//
// InitEPwm1Example - Initialize EPWM1 values
//
void InitEPwm1Example()
{
   //
   // Setup TBCLK
   //
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm1Regs.TBPRD = 1;       // Set timer period
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm1Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm1Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0x00;   // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = 0x00;

   //
   // Setup shadow register load on ZERO
   //
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   /*
   EPwm1Regs.CMPA.bit.CMPA = EPWM1_MIN_CMPA;     // Set compare A value
   EPwm1Regs.CMPB.bit.CMPB = EPWM1_MIN_CMPB;     // Set Compare B value
   */
   //
   // Set actions
   //
   EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
   EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;          // Clear PWM1A on event A,
                                                 // up count

   EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;            // Set PWM1B on Zero
   EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;          // Clear PWM1B on event B,
                                                 // up count

   //
   // Interrupt where we will change the Compare Values
   //
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 3rd event

   //
   // Information this example uses to keep track
   // of the direction the CMPA/CMPB values are
   // moving, the min and max allowed values and
   // a pointer to the correct ePWM registers
   //
   epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing
                                                 // CMPA & CMPB
   epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP;
   epwm1_info.EPwmTimerIntCount = 0;             // Zero the interrupt counter
   epwm1_info.EPwmRegHandle = &EPwm1Regs;        // Set the pointer to the
                                                 // ePWM module
   epwm1_info.EPwmMaxCMPA = EPWM1_MAX_CMPA;      // Setup min/max
                                                 // CMPA/CMPB values
   epwm1_info.EPwmMinCMPA = EPWM1_MIN_CMPA;
   epwm1_info.EPwmMaxCMPB = EPWM1_MAX_CMPB;
   epwm1_info.EPwmMinCMPB = EPWM1_MIN_CMPB;
}

//
// InitEPwm2Example - Initialize EPWM2 values
//
void InitEPwm2Example()
{
   //
   // Setup TBCLK
   //
   EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD;       // Set timer period
   EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm2Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm2Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;   // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV2;

   //
   // Setup shadow register load on ZERO
   //
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   EPwm2Regs.CMPA.bit.CMPA = EPWM2_MIN_CMPA;      // Set compare A value
   EPwm2Regs.CMPB.bit.CMPB = EPWM2_MAX_CMPB;      // Set Compare B value

   //
   // Set actions
   //
   EPwm2Regs.AQCTLA.bit.PRD = AQ_CLEAR;            // Clear PWM2A on Period
   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;              // Set PWM2A on event A,
                                                   // up count

   EPwm2Regs.AQCTLB.bit.PRD = AQ_CLEAR;            // Clear PWM2B on Period
   EPwm2Regs.AQCTLB.bit.CBU = AQ_SET;              // Set PWM2B on event B,
                                                   // up count

   //
   // Interrupt where we will change the Compare Values
   //
   EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;       // Select INT on Zero event
   EPwm2Regs.ETSEL.bit.INTEN = 1;                  // Enable INT
   EPwm2Regs.ETPS.bit.INTPRD = ET_3RD;             // Generate INT on 3rd event

   //
   // Information this example uses to keep track
   // of the direction the CMPA/CMPB values are
   // moving, the min and max allowed values and
   // a pointer to the correct ePWM registers
   //
   epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP;   // Start by increasing CMPA
   epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN; // and decreasing CMPB
   epwm2_info.EPwmTimerIntCount = 0;               // Zero the interrupt
                                                   // counter
   epwm2_info.EPwmRegHandle = &EPwm2Regs;          // Set the pointer to the
                                                   // ePWM module
   epwm2_info.EPwmMaxCMPA = EPWM2_MAX_CMPA;        // Setup min/max
                                                   // CMPA/CMPB values
   epwm2_info.EPwmMinCMPA = EPWM2_MIN_CMPA;
   epwm2_info.EPwmMaxCMPB = EPWM2_MAX_CMPB;
   epwm2_info.EPwmMinCMPB = EPWM2_MIN_CMPB;
}

//
// InitEPwm3Example - Initialize EPWM3 values
//
void InitEPwm3Example(void)
{
   //
   // Setup TBCLK
   //
   EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
   EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD;       // Set timer period
   EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
   EPwm3Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
   EPwm3Regs.TBCTR = 0x0000;                  // Clear counter
   EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
   EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

   //
   // Setup shadow register load on ZERO
   //
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

   //
   // Set Compare values
   //
   EPwm3Regs.CMPA.bit.CMPA = EPWM3_MIN_CMPA;  // Set compare A value
   EPwm3Regs.CMPB.bit.CMPB = EPWM3_MAX_CMPB;  // Set Compare B value

   //
   // Set Actions
   //
   EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;         // Set PWM3A on event B, up count
   EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR;       // Clear PWM3A on event B,
                                              // up count
   EPwm3Regs.AQCTLB.bit.ZRO = AQ_TOGGLE;      // Toggle EPWM3B on Zero

   //
   // Interrupt where we will change the Compare Values
   //
   EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;  // Select INT on Zero event
   EPwm3Regs.ETSEL.bit.INTEN = 1;             // Enable INT
   EPwm3Regs.ETPS.bit.INTPRD = ET_3RD;        // Generate INT on 3rd event

   //
   // Start by increasing the compare A and decreasing compare B
   //
   epwm3_info.EPwm_CMPA_Direction = EPWM_CMP_UP;
   epwm3_info.EPwm_CMPB_Direction = EPWM_CMP_DOWN;

   //
   // Start the count at 0
   //
   epwm3_info.EPwmTimerIntCount = 0;
   epwm3_info.EPwmRegHandle = &EPwm3Regs;
   epwm3_info.EPwmMaxCMPA = EPWM3_MAX_CMPA;
   epwm3_info.EPwmMinCMPA = EPWM3_MIN_CMPA;
   epwm3_info.EPwmMaxCMPB = EPWM3_MAX_CMPB;
   epwm3_info.EPwmMinCMPB = EPWM3_MIN_CMPB;
}

//
// update_compare - Update the compare values for the specified EPWM
//
void update_compare(EPWM_INFO *epwm_info)
{
   //
   // Every 10'th interrupt, change the CMPA/CMPB values
   //
   if(epwm_info->EPwmTimerIntCount == 10)
   {
       epwm_info->EPwmTimerIntCount = 0;

       //
       // If we were increasing CMPA, check to see if
       // we reached the max value.  If not, increase CMPA
       // else, change directions and decrease CMPA
       //
       if(epwm_info->EPwm_CMPA_Direction == EPWM_CMP_UP)
       {
           if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA < epwm_info->EPwmMaxCMPA)
           {
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
           }
           else
           {
              epwm_info->EPwm_CMPA_Direction = EPWM_CMP_DOWN;
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
           }
       }

       //
       // If we were decreasing CMPA, check to see if
       // we reached the min value.  If not, decrease CMPA
       // else, change directions and increase CMPA
       //
       else
       {
           if(epwm_info->EPwmRegHandle->CMPA.bit.CMPA == epwm_info->EPwmMinCMPA)
           {
              epwm_info->EPwm_CMPA_Direction = EPWM_CMP_UP;
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA++;
           }
           else
           {
              epwm_info->EPwmRegHandle->CMPA.bit.CMPA--;
           }
       }

       //
       // If we were increasing CMPB, check to see if
       // we reached the max value.  If not, increase CMPB
       // else, change directions and decrease CMPB
       //
       if(epwm_info->EPwm_CMPB_Direction == EPWM_CMP_UP)
       {
           if(epwm_info->EPwmRegHandle->CMPB.bit.CMPB < epwm_info->EPwmMaxCMPB)
           {
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB++;
           }
           else
           {
              epwm_info->EPwm_CMPB_Direction = EPWM_CMP_DOWN;
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB--;
           }
       }

       //
       // If we were decreasing CMPB, check to see if
       // we reached the min value.  If not, decrease CMPB
       // else, change directions and increase CMPB
       //
       else
       {
           if(epwm_info->EPwmRegHandle->CMPB.bit.CMPB ==
              epwm_info->EPwmMinCMPB)
           {
              epwm_info->EPwm_CMPB_Direction = EPWM_CMP_UP;
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB++;
           }
           else
           {
              epwm_info->EPwmRegHandle->CMPB.bit.CMPB--;
           }
       }
   }
   else
   {
      epwm_info->EPwmTimerIntCount++;
   }

   return;
}

//
// End of file
//

Clock settings I changed and code changes highlighted in the following images>

Above image is oscilloscope print connected on GPIO25 pin.

Let me know if my understanding and configurations are wrong. 

Is this the maximum frequency we can obtain with this EPWM up counting?

Thanks,

Akshay

Part Number:LM5122-Q1

Tool/software: WEBENCH® Design Tools

Hello,

Is there a BXL symbol file available for LM5122-Q1?  I could not find it on the product folder or webench.ti.com/cad/ search portal.  One of our customers is requesting this.

Thanks,
Alan

Part Number:TPS92518HV-Q1

Tool/software: WEBENCH® Design Tools

Hello,

Is there a BXL symbol file available for TPS92518HV-Q1?  I could not find it on the product folder or webench.ti.com/cad/ search portal.  One of our customers is requesting this.

Thanks,
Alan

Part Number:PROCESSOR-SDK-AM335X

Tool/software: Linux

Hi,

In a  previous thread I asked how to stop the kernel from reconfiguring the GPMC parameters set by the bootloader (the thread was locked due to inactivity, I had to stay away from work and just got around recently to investigating this issue further). I received a reply telling me to use the "ti,no-reset-on-init" setting in the .dts file, but this seems to cause the kernel to crash because it can't mount /.

Original .dts node:

&gpmc {
   status = "okay";
   ranges = <0 0 0x01000000 0x10000000>;  /* CS0: 256MB */
   nand@0,0 {
      compatible = "ti,omap2-nand";
      reg = <0 0 8>; /* CS0, offset 0, IO size 4 */
      interrupt-parent = <&gpmc>;
      interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                   <1 IRQ_TYPE_NONE>;  /* termcount */
      rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
      ti,nand-ecc-opt = "bch8";
      ti,elm-id = <&elm>;
      nand-bus-width = <8>;
      gpmc,device-width = <1>;
      gpmc,sync-clk-ps = <0>;
      gpmc,cs-on-ns = <0>;
      gpmc,cs-rd-off-ns = <25>;
      gpmc,cs-wr-off-ns = <25>;
      gpmc,adv-on-ns = <0>;
      gpmc,adv-rd-off-ns = <25>;
      gpmc,adv-wr-off-ns = <25>;
      gpmc,we-on-ns = <0>;
      gpmc,we-off-ns = <10>;
      gpmc,oe-on-ns = <0>;
      gpmc,oe-off-ns = <10>;
      gpmc,access-ns = <20>;
      gpmc,rd-cycle-ns = <25>;
      gpmc,wr-cycle-ns = <25>;
      gpmc,wr-access-ns = <0>;
      gpmc,wr-data-mux-bus-ns = <0>;
      /* MTD partition table */
      /* All SPL-* partitions are sized to minimal length
       * which can be independently programmable. For
       * NAND flash this is equal to size of erase-block */
      #address-cells = <1>;
      #size-cells = <1>;
      partition@0 {
         label = "SPL";
         reg = <0x00000000 0x000020000>;
      };
      partition@1 {
         label = "SPL.backup1";
         reg = <0x00020000 0x00020000>;
      };
      partition@2 {
         label = "SPL.backup2";
         reg = <0x00040000 0x00020000>;
      };
      partition@3 {
         label = "SPL.backup3";
         reg = <0x00060000 0x00020000>;
      };
      partition@4 {
         label = "u-boot";
         reg = <0x00080000 0x00080000>;
      };
      partition@5 {
         label = "u-boot.backup1";
         reg = <0x00100000 0x00080000>;
      };
      partition@6 {
         label = "u-boot.backup2";
         reg = <0x00180000 0x00080000>;
      };
      partition@7 {
         label = "u-boot.backup3";
         reg = <0x00200000 0x00080000>;
      };
      partition@8 {
         label = "kernel";
         reg = <0x00280000 0x00500000>;
      };
      partition@9 {
         label = "fs";
         reg = <0x00780000 0x01400000>;
      };
      partition@10 {
         label = "drivers";
         reg = <0x01b80000 0x004e0000>;
      };
      partition@11 {
         label = "dtb";
         reg = <0x02060000 0x00020000>;
      };
      partition@12 {
         label = "app";
         reg = <0x02080000 0x00a00000>;
      };
      partition@13 {
         label = "upgd";
         reg = <0x02a80000 0x00200000>;
      };
      partition@14 {
         label = "hwinfo";
         reg = <0x02c80000 0x00100000>;
      };
      partition@15 {
         label = "dmin";
         reg = <0x02d80000 0x00a00000>;
      };
      partition@16 {
         label = "dgen";
         reg = <0x03780000 0x0c880000>;
      };
   };
};

Modified .dts node:

&gpmc {
    status = "okay";
    ranges = <0 0 0x01000000 0x10000000>;  /* CS0: 256MB */
    ti,no-reset-on-init;
    nand@0,0 {
       compatible = "ti,omap2-nand";
       reg = <0 0 8>; /* CS0, offset 0, IO size 4 */
       interrupt-parent = <&gpmc>;
       interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
                    <1 IRQ_TYPE_NONE>;  /* termcount */
       rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
       ti,nand-ecc-opt = "bch8";
       ti,elm-id = <&elm>;
       nand-bus-width = <8>;
       gpmc,device-width = <1>;
       /* MTD partition table */
       /* All SPL-* partitions are sized to minimal length
        * which can be independently programmable. For
        * NAND flash this is equal to size of erase-block */
       #address-cells = <1>;
       #size-cells = <1>;
       partition@0 {
          label = "SPL";
          reg = <0x00000000 0x000020000>;
       };
       partition@1 {
          label = "SPL.backup1";
          reg = <0x00020000 0x00020000>;
       };
       partition@2 {
          label = "SPL.backup2";
          reg = <0x00040000 0x00020000>;
       };
       partition@3 {
          label = "SPL.backup3";
          reg = <0x00060000 0x00020000>;
       };
       partition@4 {
          label = "u-boot";
          reg = <0x00080000 0x00080000>;
       };
       partition@5 {
          label = "u-boot.backup1";
          reg = <0x00100000 0x00080000>;
       };
       partition@6 {
          label = "u-boot.backup2";
          reg = <0x00180000 0x00080000>;
       };
       partition@7 {
          label = "u-boot.backup3";
          reg = <0x00200000 0x00080000>;
       };
       partition@8 {
          label = "kernel";
          reg = <0x00280000 0x00500000>;
       };
       partition@9 {
          label = "fs";
          reg = <0x00780000 0x01400000>;
       };
       partition@10 {
          label = "drivers";
          reg = <0x01b80000 0x004e0000>;
       };
       partition@11 {
          label = "dtb";
          reg = <0x02060000 0x00020000>;
       };
       partition@12 {
          label = "app";
          reg = <0x02080000 0x00a00000>;
       };
       partition@13 {
          label = "upgd";
          reg = <0x02a80000 0x00200000>;
       };
       partition@14 {
          label = "hwinfo";
          reg = <0x02c80000 0x00100000>;
       };
       partition@15 {
          label = "dmin";
          reg = <0x02d80000 0x00a00000>;
       };
       partition@16 {
          label = "dgen";
          reg = <0x03780000 0x0c880000>;
       };
    };
};

Is this modification correct?

Regards,

Guilherme

Part Number:LAUNCHCC3220MODASF

Hello, I've been reading SWPU332 and would like to confirm a few things:

The root-ca signatures are kept in the certificate catalog (provided by TI).  The user must choose which root CAs they're using, and include it via uniflash (which is effectively an abbreviated certificate catalog).

The code-signing cert I get from, say godaddy, would be a trusted-root-ca. I would need to include this along with godaddy's root-ca-cert in the uniflash build.

For development, I can get away with using just the dummy-root-ca since the key is provided, yes?

For HTTPS server, I would also need another trusted-root-ca, correct?

For development, is it possible to use the dummy-root-ca+key for both code signing and HTTPS server?

Thanks 

Chris

Part Number:TM4C123GH6PZ

I have a custom board with the above TIVA part.  We have an application that is currently in production and reliable.  The goal is to implement a flash bootloader that will allow application updates via the CAN bus (which is the primary comm link on the board.  

My though was to implement this in several steps:

1.  Use the TI serial_boot example found in the TivaWare examples to start. 

2. Verify that  the bootloader  hands over control to the application and the application functions properly.

3. Program the application via the serial

3. Using the serial_boot example as a baseline, modify the bootloader to use the CAN bus in place of the serial.

The problem is that I can't beyond step 1.  The bootloader and application have been modified to reflect the correct memory spaces.  

The bl_config.h file in the boot_serial project has been modified to include:

#define VTABLE_START_ADDRESS    0x2800

#define APP_START_ADDRESS       0x2800

The file tm4c123gh6pz_startup.cmd in the application was modified:

#define APP_BASE_ADDR 0x00002800
#define RAM_BASE_ADDR 0x20000000

MEMORY
{
FLASH (RX) : origin = APP_BASE_ADDR, length = 0x0003d800
SRAM (RWX) : origin = 0x20000000, length = 0x00008000
}

/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M4_T_le_eabi.lib */

/* Section allocation in memory */

SECTIONS
{
.intvecs: > APP_BASE_ADDR
.text : > FLASH
.const : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH

.vtable : > RAM_BASE_ADDR
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM
}

Using the UniFlash application, I load the boot_serial.bin to address 0x0000 and the application to address 0x2800

My expectation is that the bootloader would run, there is no serial input and would transfer control to the application at start address 0x2800 but it's not happening.  I am basing this on the LED indicator on the board that is lit immediately upon the application init.

My questions are:

1. Are my expectations incorrect?  Is there something I am missing?  Should the example boot_serial not start the application?

2. What is the best approach to debugging the bootloader?  I'm using CCS7 as my development environment and the XDS2xx USB emulator.

Thanks!

Part Number:TMS570LS1227

Hi,

I've been trying to debug my JTAG connection issues for a few days now. I've looked through the 'Debugging JTAG Connectivity Problems' page and read a lot of the forum questions here.

I have a custom board with the TMS570LS1227, and I'm using an XDS110 debug probe to connect to CCS v7.4.0. When I run the JTAG integrity scan, the JTAG IR Integrity and JTAG DR Integrity scan tests both succeed with no failed tests. I tried to debug a program but ran into this error:

I followed these instructions and launched just the target configuration file in a debug session:

1] Start CCS
2] Open Target Configurations Window.
3] Right click on your target configuration for your device.
4] Click on Launch Selected Configuration.
5] A new window (Debug) should be open.
6] Right click on the entry in this window and select Show all Core.
7] Right click on "Icepick" and select "Connect"
8] Icepick should be connected now.

9) In CCS Go to Run->Reset->System Reset to reset the device

10] right click on "DAP" and select "Connect"
11] DAP should be connected now.

12] Right Click on Cortex_R4 and select "Connect"

13) if you are unable to connect to the CPU, it will give you error and ask you to retry.

I am not able to get past connecting to the ICE-PICK however. I receive this error: "

IcePick: Error connecting to the target: (Error -2131 @ 0x0) Unable to access device register"

I've validated the debugger and the adapter connections by using another similar board using a TMS570LS1224. That one works fine and is able to debug, connect, and load programs.

Is my MCU locked or dead? The board draws about 30mA; nRST, nPORRST, and nERROR are all high and do not toggle when scoped. The crystal waveform is also similar to waveforms from working boards.

Do you have any suggestions for proceeding?

Part Number:TPS7A39

Hi,

I want to use the TPS7A39 to regulate two 3.7V batteries to +-3.3V. According to the typical application circuit and tables attached (extracted from the device's datasheet), the resistors for this would be R1p = 17.8k, R2p = 10k, and R1n = 28k, R2n = 10k.

My question is, would it be possible to obtain the same 3.3V output with another ratio of resistors? According to the formula, using the suggested values of R1p and R2p, I can obtain the value of VNR/SS, and thus I can get different values of resistors that would, in paper, get the same 3.3V (or very close to it). The same can be done for the negative supply. For example, using R1p = 17.8k, R2p = 10k, and R1n = 28k, R2n = 10k, I got:

3.3 = VNR/SS*(1+17.8/10) => VNR/SS = 1.18. So, trying to adjust to my available SMD resistor values, I got: R1p = 12k and R2p =6.8k, giving a Vout = 3.28V.

-3.3V = VNR/SS*(-28k/10k) => VNR/SS = 1.18 (should've expected that it would be the same). And trying to adjust the values to my resistors, I got R1n 22k = and R2n = 7.8k, giving a Vout = -3.32V.

Is this calculation going to output the desired voltage if connected to the circuit attached? Or do I have to use the specified ones that are on the table?

Thanks in advance,

Roberto

Part Number:MSP430FR5969-SP

In another thread in Oct 2018 it was mentioned that data had been taken referencing the MSP430 SEU susceptibility.  It was stated that the report would be available in about a month, but I have not seen the report any place on the website.  Is this report available?  We would like to compare it to some of our own results.  

Part Number:TMS570LS1224

Tool/software: Code Composer Studio

Good day,

we want to interface a TMS570LS1224 with a GPS receiver over UART. Therefore we use a baud rate of 921600 baud.

In order to have an accurate baud rate, we use the SCI2 module (LIN in SCI mode) where we have the possibility to fine tune the baud rate. (The module is configured to act in functional mode (not GIO mode)):

    /* baud rate fine tuning */
    /* bring the module into reset state */
    scilinREG->GCR1 &= ~( 0x80U );

    /* Formula:
     * P = prescaler part
     * M = 4 bit fractional divider part
     * VCLK_freq / ( 16 * ( P + 1 + ( M / 16 ) ) ) */

    scilinREG->BRS  = 0U;

    /* baud rate currently to: ~921600 baud */

    /* baud rate prescaler */
    scilinREG->BRS |= ( 4U <<  0U );

    /* 4-bit fractional divider selection */
    scilinREG->BRS |= ( 7U << 24U );

    /* enable the module again */
    scilinREG->GCR1 |= 0x80U;

This baud rate business is working quite fine so far, but the signals coming from the GPS receiver (RX) are not properly pulled to 0V, so no data is received on the TMS570LS1224 side.

To clarify I captured the signals with this strange behavior:

Yellow: Signals from TMS570LS1224 towards GPS receiver

Green: Signals from GPS receiver towards TMS570LS1224

If I disconnect the RX pin on the TMS570LS1224 side and capture the signals again, they are properly pulled to 0V as depicted below:

Yellow: Signals from TMS570LS1224 towards GPS receiver

Green: Signals from GPS receiver (but not connected to the RX pin on the TMS570LS1224).

... absolutely no clue what could be the issue here!?!??? Any hints / suggested solutions would be very much appreciated.

Thank you and best regards ...

P.

Part Number:MSP430FR5989

I have an aplication that uses the ESI from the MSP430FR5989 for rpm counter using 3 LCs. The sensing mechanism is fine and stable, but i had to write an algorithm for constant recalibration.

I would like to remove this "background calibration". The first thing i did was to use the comparator offset cancellation procedure (37.2.1.7 from family guide) and make sure there is no drift related to temperature  in the SMCLK that is configured to be used by the ESI. This is working because i didnt notice any drift in each LC oscillation when fast changing the temperature in the board.

But the temperature is still heavily influencing the ESI. The 0.2 uV/C that is expected in the comparator offset seems to be much higher, even higher than when not using the autozeroing procedure....

Is any other parameter that could be affected by temperature? I discarded the LC  and the SMCLK oscillator, i even put a TXCO directly in HFX to make sure there is no drift in the clock used by the ESI.

Thanks !

Part Number:CC2640R2F

Tool/software: TI-RTOS

Hi,

We have a CC2640R2F custom board with Adesto AT25XE041B external flash. I managed to integrate extFlash.h driver from simple_peripheral_cc2640r2_oad_offchip example, but the thing is, that we need to use SPIFFS and SPIFFS uses NVS.

To make extFlash driver work, I had to:

• change "Read Manufacturer and Device ID" pin from 0x90 to 0x9F,
• modify ExtFlash_readInfo() to send only one byte
• add AT25XE041B manfId (0x1F) and devId (0x44) to flashInfo
• implement ExtFlash_global_unprotect function, since this extflash seems to be write protected by default.

Now I should do similar thing with NVS, but I am bit lost. 

Driver implementation seems to be in NVSSPI25X.h, but there is no "Read Manufacturer and Device ID" logic nor protect/unprotect logic.

Should I be able to make NVS work, without these somehow? Or how should I implement them?