Part Number:PCA9306

Hi team,

     When customer use PCA9306 device, if they power down VREF1 1.8V and power up VREF2 3.3V, whether would PCA9306 device have leakage current through CAN or power pin?

Best Regards

Zhengquan Lu

Part Number:LM48511

Hi TI expert

  Please help us identifying if there are design issues on LM48511 PV1 which is power supply for speaker

attached spreadsheet is my test data, you can take a look, and help me to check if there are design issues

(Please visit the site to view this file)

Part Number:DP83822I

Hi,

I've got a DP83822I on a board with a Cyclone V (RGMII) - in U-BOOT its failing to auto-negotiate (the Auto-Negotiation Complete bit in reg 0x0001 is never getting set). I'm seeing reg 0x0005 updating with Link Partner information when the board is either connected to a PC, connected with an external loop-back on the RJ45 or configured for analogue loop-back with the BIST register - so it looks like somethings happening. Can you suggest what I need to look at - its not in reset and its got a 25MHz clock. From a similar post these are the registers that were requested:

0x00 = 0x1000
0x04 = 0x01E1
0x05 = 0xC1E1
0x10 = 0x4002
0x17 = 0x0261
0x19 = 0x8021
0x467 = 0x2001
0x468 = 0x4000

Kind regards,

Dave

Part Number:AM4372

Tool/software: TI-RTOS

Hi .

#1. I notice there are 2 folder:

     C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash

     C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uartAppLoader

     What's the purpose of those 2 folder?

#2. If we want to uniflash to flash the customer PCB, we need to make the "uniflash" folder, right?

    So, how is the exactly command for building the QSPI Flash boot loader for Uniflash working on AM437?

#3. I type the command as below, but it will show me the error, how to solve?

C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash>gmake SOC=AM437x
compiling C:/TI/pdk_am437x_1_0_13/packages/ti/starterware/soc/armv7a/gcc/sbl_init.S ...
linking C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/xmodem.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/u
art_main.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/qspi.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/
soc.o C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/obj/idkAM572x/sbl_init.ao into C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/bin/idkAM
572x/uart_idkAM572x_flash_programmer.out ...
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/soc/am572x/linker.cmd: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/lib/idkAM572x/a9/release/ti.board.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/drv/uart/lib/am572x/a9/release/ti.drv.uart.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/drv/spi/lib/am572x/a9/release/ti.drv.spi.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/csl/lib/am572x/a9/release/ti.csl.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/osal/lib/nonos/am572x/a9/release/ti.osal.aa9fg: No such file or directory
arm-none-eabi-gcc.exe: error: C:/TI/pdk_am437x_1_0_13/packages/ti/board/lib/idkAM572x/a9/release/ti.board.aa9fg: No such file or directory
gmake: *** [C:/TI/pdk_am437x_1_0_13/packages/ti/board/utils/uniflash/bin/idkAM572x/uart_idkAM572x_flash_programmer.out] Error 1

C:\TI\pdk_am437x_1_0_13\packages\ti\board\utils\uniflash>

BR Rio

Part Number:MSP430F67791A

Hi,

Can anybody tell me the download link for TIDMTHDREADING. I am not able to find it on site. 

Thanks.

Part Number:AM5716

Hi Experts,

I'd like to identify that WDT_RST is occurred when AM571x is reset. However, due to the circuit that avoids Errata i862, it seems that PRM_RSTST is always '1' (GLOBAL_COLD_RST) after any resets.

Do you have a good way to identify WDT_RST? Also, what does the following method described in Errata specifically mean? What should I do?

"To maintain some visibility software may be able to store information in PMIC BACKUP or other PMIC registers."

Regards,
Kzk

Part Number:LDC1614

Hi!

Based on evaluation board LDC1614EVM I have tried to make communication between my MCU and LDC1614.

Generally I have problem to understand how set the main address of the LDC for write and read. The "addr pin" in my solution is connected to the ground so the LDC adress is set to 0x2A. 

According to the datashet the serial bus address has a bit that is responsible for R/W. How I can change the adres for write or read? Below I am sending my code for read data from LDC. In this case the resposne is 0x2A and 0x2A.

TWI_start();
TWI_write(0x2A); // ADDR do GND	
TWI_write(0x00); 
TWI_start();
	
TWI_write(0x2A); // ADDR do GND	
bajt0=TWI_read(ACK);
bajt1=TWI_read(ACK);
TWI_stop();
		
uart_putint(bajt0,16);
uart_puts("    ");
uart_putint(bajt1,16);
uart_puts("\n");		



Also I am sending a configuration of the LDC:

	//RCOUNT 0
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x08);	
	TWI_write(0x04);	
	TWI_write(0xD6);
	TWI_stop();
	_delay_ms(10);
			
	//Settlecount 0
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x10);
	TWI_write(0x00);
	TWI_write(0x0A);
	TWI_stop();
	_delay_ms(10);	
	
	//Clock Dividers 0
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x14);
	TWI_write(0x10);
	TWI_write(0x02);
	TWI_stop();		
	_delay_ms(10);		
	
	//Error config
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x19);
	TWI_write(0x00);
	TWI_write(0x00);
	TWI_stop();		
	_delay_ms(10);	
	
	//MUX Config
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x1B);
	TWI_write(0x02);
	TWI_write(0x0C);
	TWI_stop();				
	_delay_ms(10);
	
	//Drive current 0
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x1E);
	TWI_write(0x90);
	TWI_write(0x00);
	TWI_stop();
	_delay_ms(10);	
	
	//Config
	TWI_start();
	TWI_write(adr); // ADDR do GND
	TWI_write(0x1A);
	TWI_write(0x14);
	TWI_write(0x01);
	TWI_stop();	

Part Number:CC2640R2F

In the table in "How to certify your BT product" the under the RF-PHY IXIT references there are no values for RF-PHY 13 to 16 , I guess the values for inband image frequency and n-value for IMD will be the same, is that so?

Part Number:CC3220MOD

Tool/software: Code Composer Studio

I connected the xsd100 to PC, and connected the PCB to xds110. I also connected the power supply to PCB with 4V. 

The ccxml file has been setup as showed below. When I clicked ’test connection’ in CCS, an error occurred. 

I also used multimeter to test pin_V3V3 of  the JTAG on PCB, it showed 3.3V.

Do you know what the meaning of ‘ JTAG  IR  and DR scan-path cannot circulate bits’ ?  And what should I do to solve this problem?

Part Number:TPS92662-Q1

Dear Sir/Ms.

I would like to ask if the TPS92662 can be connected as shown below, through the DEVID segment in the communication protocol.
DEV_ID[4:0]. Set as follows:
RH:
TPS92662 : DEV_ID[4:0]0x01
MCU: DEV_ID[4:0]0x03

LH:
TPS92662 : DEV_ID[4:0]r0x02
MCU: DEV_ID[4:0]0x04

Best Regards,

Kami Huang

Part Number:TMS320F28377D

Tool/software: Code Composer Studio

Hello,

I am using a TIDM-HV-1PH-DCAC for low voltage applications and this means that I am operating it less than the minimum threshold for when guiVrms and guiIrms appears.

I have found this forum post (https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/678262?CCS-TMS320F28377D-Problems-with-running-buid-in-TIDM-HV-1PH-DCAC-voltage-source-inverter-reference-design-project).

I am also not sure if I should be changing a setting somewhere else maybe.

Part Number:SN74HC132

Hello, our customer received 1000 pieces P/N: SN74HC132N with Date Code 1816 from us, but claims the coloring of the leads and solderability:

----- 

SaNu the pins are "tapped" (surface brown to black-brown).

The solderability according to IPC-A-610 EN Edition E-2010 Chapters 5.2.4 and 5.2.6 or IPC-T-50 is not given.

Test conditions Solderability:=> Soldering bath with 245C => Test / immersion time 3s=> flux Interflux 2005 => Also the examination by soldering iron method did not bring sufficient wetting (min 95%) according to J-STD-003 chapter 4.2.1.5.2 => The IC's cannot be used in this form.

-----

Can you possibly advise if the discoloring of the parts can be the reason for the solder problems? Per datasheet these parts are not MSL sensitive. Would they require any specific pre-treatment before soldering?

What additional details would be required to look into this issue?

Thank you.

Part Number:AM5728

Tool/software: Code Composer Studio

Hi,

I want to run the No OS (Bare Metal) Example on the MINI5728. 

After I right click CortexA15_0 and select connect target., CCS prompts that Break at address "0x3f9f0" with no debug information available, or outside of program code.

Console prints the following information：

Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG1.1 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Two EMIFs in interleaved mode - (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

How should I solve this problem?

Thank you!

Hi, 

There is only typ number for the Maximum output power. Is there the Max/Min number? 

Thanks.

BR. Albin

Part Number:UCC28019A

can I get reference design for ucc28091a PFC ?

I am unable to get this ic in tina tool

Part Number:DRA72

Tool/software: Linux

Hi,

The customer want to add TJA1101 support in VSDK0305. The default is RGMII, but the customer board interface is MII. I checked in E2E, and found similar issue as below link.

Please check and give some suggestions how to modify the driver to add TJA1101 support in VSDK0304?

First we can add support in linux? then we can porting to NDK.

Best Regards,

Fredy

Part Number:CC3120BOOST

Hi,

SDK :  

simplelink_sdk_wifi_plugin_2_30_00_10

simplelink_msp432p4_sdk_2_30_00_14

The service package to the Flash SPI is sp_3.9.0.6_2.0.0.0_2.2.0.6.bin.

Board use：

MSP432LaunchPad 

CC3120BOOST

CC3120  ping PC network：

PC ping CC3120 network

Is this network delay normal? 

What is the cause of the high network latency?

Is there any way to reduce it?

I hope I can get some help.

Thank you.

Andre

Part Number:LAUNCHXL-CC2640R2

Tool/software: Code Composer Studio

Hello,

I have my CC2640R2 LaunchPad. I am working with CC2640R2 adcbufcontinuous and rfWsnNode sample programs written by TI using CCS.

In my situation, there are two CC2640R2 LaunchPad, one acts as a transmitter and one acts as a receiver. Suppose I have a sine wave signal coming into one of the ADC pins of the CC2640R2 transmitter, after adc, I want the data transmitted wirelessly to the CC2640 receiver. I know that negative values of sine wave cannot be read by the launchpad, I may do the half wave conversion at this stage first.

I tried to incorporate CC2640R2 adcbufcontinuous sample codes into CC2640R2 rfWsnNode sample codes, but due to the lack of program knowledge, I failed many times.

Therefore, I am writing to ask are there any tutorials or guide for me so that I can perform this task?

Thanks for your help!

Part Number:CC2530

Hi folks,

We have a network with multiple (around 15 ZED's and 2 routers) ZED's (running zstack 3.0.1). In our code, we maintain a reboot count variable. This variable is stored in the NV RAM and is incremented at the start of every program cycle (every reboot). We can see multiple device announcements in our controller (ZC) logs, but the reboot count stays the same. Is there any particular reason for the ZED to issue this message multiple times without rebooting?

Thanks,

Ashwin N

Part Number:CC1310

Hi

Why CC1310 on 433M max output power is +15dBm?

But it's +14dBm at 868 and 915MHz? Thanks.