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DS90UB954-Q1: How to check the margin by manual operation

February 4, 2019, 3:17 am
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Part Number:DS90UB954-Q1

Hi team,

I experimentally done the manual margin analysis using EVM.

I refer to the document of the link below.

http://www.ti.com/lit/an/snla301/snla301.pdf

http://www.ti.com/lit/ug/snlu243/snlu243.pdf

First, I got the results using the margin analysis of the GUI and confirmed whether the same result can be obtained by manual setting.

The results obtained by GUI margin are as follows.

Therefore, there is a doubt about the error check register and its procedure.

In the document, registers whose errors should be confirmed are described as 0x4D[5:2] and 0x4E[5].

However, as a result of manual verification, when checking 0x4D [5: 2] and 0x4E [5], these registers remain 0 if SP is small or large.

The results at that time are as follows.

When SP is close to 0 or close to 14, register 0x4D is 0x00 and 0x4E is 0x02 in many cases.

That is, both PASS and LOCK are 0, and communication is not established.

Empirically, if it is UNLOCK status, 0x4E [2]: CABLE FAULT seems to be detected.

Also, I think that this register corresponds to the following FPD-LINK III clock, should this register also be checked?

Or will it be necessary to change the SP from the condition of stable locking?

We would like to establish a valid manual verification method.

Best regards,

Tomoaki Yoshida

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TMS320F28379D: C2000Ware driverlib Flash examples

February 4, 2019, 3:17 am
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Part Number:TMS320F28379D

Hi,

I haven't found Flash module (from C2000Ware driverlib) examples. I want to call the next APIs:

 - Flash_enableECC (uint32_t eccBase).

 - Flash_disableECC (uint32_t eccBase).

 - Flash_claimPumpSemaphore (uint32_t pumpSemBase, Flash_PumpOwnership wrapper).

 - Flash_releasePumpSemaphore (uint32_t pumpSemBase).

And I am not sure of what is the right value of both "eccBase" and "pumpSemBase".

Can anyone tell me either where can I find Flash module examples (from C2000Ware driverlib) where those APIs are called or what is the right value of those 2 parameters?

Thanks in advance!

Best regards,

Adria

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Power Save mode of TLC5929

February 4, 2019, 3:20 am
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We have questions about Power Save mode of TLC5929.


Is the remove condition from Power save mode only SCLK input?
Are this IC affected by the status of LAT and DATA when we want to remove Power Save mode?

Can this IC remove Power Save mode by SCLK input when LAT and DATA are HIGH?

Does this IC keep Power Save mode as long as SCLK isn't input even if LAT or DATA is HIGH?



Best regards,


Takahiro Nishizawa


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RTOS/CC2640R2F: support for full L2CAP API still missing in SDK 2.40

February 4, 2019, 3:25 am
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Part Number:CC2640R2F

Tool/software: TI-RTOS

Hello,

while L2CAP CoC offer some support since SDK 2.30, any useful support is still missing in 2.40.

I'm succesfully using lower level APIs like `L2CAP_SendSDU` but the whole purpose of L2CAP CoC is defeated when APIs like `L2CAP_SendData` are not available.

There is no streaming support without those functions. What are your plans to support this?

Or am I missing something vital?

Also on the receiving side, I only managed to receive data packages up to 255 bytes.

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LM339: LM339 or TL074(Selection)

February 4, 2019, 3:29 am
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Part Number:LM339

Hi,

I have an application(Solar inverter) where I have to sense AC/DC voltages, current and generate reference voltages (1.65V and 2.5V). I was confused between LM339 and LM074 quad amplifier.

Also, on what parameter I should compare amplifiers when using in a solar application.

Regards,

Archit

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TMS320C6678: EMIF16 NOR Boot with Extended Ready pin

February 4, 2019, 3:30 am
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Part Number:TMS320C6678

Hi,

My customer is asking that which EMIF16 EMIFWAIT pin is valid and what is the polarity during the NOR Boot operation when 'wait enable' is being enabled on BOOT parameter.

I've checked the ROM bootloader implementation, but it looked that it did not set AWCCR register at all (The actual ready pin selection and its polarity should be set via this register). The bootloader just set A1CR register to use EM bit-filed if BOOT parameter has been set as 'Wait Enable' enabled. 

This implies that AWCCR register keeps its default state during EMIF16 Boot operation, but what i want to clarify here is that AWCCR CS2_WAIT bitfield (i believe this is for actual EMIF16 wait selection on C6678) does not mention about the default value. Can you clarify ?

Best Regards,

NK

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CC1310: Frequency 868MHz

February 4, 2019, 3:30 am
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Part Number:CC1310

Good morning, we have a system which is based on the CC1310 working at frequency 868MHz.

I have some doubts about the frequency, I hope you can help me about this.

I read in some examples that it is suggested, in case of need, to change the frequency: (http://dev.ti.com/tirex/content/simplelink_academy_cc13x0sdk_1_13_03_11/modules/prop_02_wsn_example/prop_02_wsn_example.html.

This feature can be useful also for our system, in order to avoid collisions between two different systems. It is not clear which range of frequencies can be used, even if, according to the Italian law, I think it should be from 868,0 Mhz to 868,6 MHz, in order to have  TxPower = 25mW and duty cycle = 1%.

The main not clear  aspect is which distance between two different frequencies can be configured. The example suggests 100KHz, but is this the real distance configurable?

A last question: is it possibile to change the frequency run time by EasyLink API?

Thanks in advance, Andrea

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DP83848J: Power up Reset X1 clock requirements.

February 4, 2019, 3:36 am
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Part Number:DP83848J

Hi,

A question on the DP83848J chip.

Q: Is it required that the X1 25 MHz clock is started/applied within a specific time period after the PHY chip is powered up?

In our case the X1 clock is applied after approx. 3 seconds after that the PHY chip is powered up.
After that the X1 clock is applied on to the PHY chip we implement a delay of 256 ms before starting/applying the MDC (preamble) to the PHY chip.

This works without any problem most of the time the system is powered on.
But , at about a frequency of one of ca 100 system (PHY chip) power up's the MII interface of the PHY chip is not working, at the next power of the PHY chip the MII interface is working, and so on.
When the X1 clock is applied at the same time the chip powered on  this problem does not occur.

Thanks
Jan

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UCC21520: Missing or delayed gate drive signal

February 4, 2019, 3:38 am
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Part Number:UCC21520

Dear all,

I am using the UCC21520 to drive a full bridge consiting of 4 Infineon IPD60R180C7 MOSFETs with SiC diodes in parallel, see the schematic below.

The other half of the bridge is designed accordingly. Not shown in the schametic above are low impedance film capacitors supporting the +400 V rail.

The bridge shall drive a (impedance matched) coil of <1 uH with a 2 MHz pulse train for creating a magnetic field. The bridge voltage (=coil driving voltage) shall be in the range 200...800 Vpp.

I am experiencing a strange problem:

When I rise the voltage at the "+400V" supply rail, starting at a specific voltage, the last pulses start to trigger later or go missing at all. This happens already at a supply voltage of appr. 55 V, depeding on the load connected to the bridge. When no load is connected, missing pulses start already at 50 V. With a coil connected, it is 55...60 V. With a load resistor, I get similar results.

Please have a look at the scope screenshots below, depicting the missing of the last pulses of a pulse train. In the first picture, the pulses look ok.

However, with increasing voltage, the last pulses (at least of one half bridge) go missing:

As you can see, there is some ringing. My layout is probably not the very best, as the distance between driver and MOSFET are ca. 20...25 mm, but I considered all layout examples from TI. The gate resistors are close to the gate. The missing pulses start at one half bridge and with increasing voltage at the other bridge, too.

I also tried to insert ferrite beads at the gates, but the ringing at the gate got much worse. Without the snubber network, ringing gets worse, too.

The signals at the UCC21520 inputs look fine. Of course, there is some noise, but it is well below 1 Vpp.

I don't know exactly where the ringing is coming from and why the pulses get delayed.

Do you have any ideas?

Thank you very much.

Best regards

Bene

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TCI6636K2H: Checking/detecting any PRBS error on the RX side (RX PRBS Checker)

February 4, 2019, 3:40 am
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Part Number:TCI6636K2H

Dear Support team,

I am working with our custom HW which contains TI custom processor TCI6636K2H. I am using MCSDK 3.1.3.6 for this purpose. I am more interested in knowing more about PRBSChecker section.

I am aware that TI has provided a in /diag/ section which contains example API for Serdes PRBS. I have used the provided example and modified based on our requirements. As there are 6 AIF2 Lanes in the TCI6636K2H processor. As per our custom hardware requirement we are more focused in PHY-A, 4 Lanes (B8) and PHY-A, 2 Lane (B4). For our application specific stuffs there,

3x lanes go to the FPGA

3x lane to the SFP

(A)  TRANSMIT TX PRBS pattern

As per the TI Provided example I have configure the Serdes_Example_PRBSTest(SERDES_AIF2_B8) and Serdes_Example_PRBSTest(SERDES_AIF2_B4) based on my requirements. I can verify Transmitter PRBS generator. WORKS

(B)    RECEIVE RX PRBS pattern

  1. I am more interested on PRBS verification (RX) side. Is there any way to verify what’s being transmitted is being received? For example, any counter or register on the DSP side to indicate that error has occurred? I know as per the manual http://www.ti.com/lit/ug/spruho3a/spruho3a.pdfBIST_CHK_ERRORS which should be non-zero (when error occurs) in my case its always 0.

 

2. How can check/detect the error on the serdes lane at the DSP end if the FPGA is transmitting with an injected error bit as per the above mentioned setup. Is there any error counter/ or any error register at DSP end which can be used to detect the error?

 

3. Also, while debugging I found that in the reserved section of the register as per the http://www.ti.com/lit/ug/spruho3a/spruho3a.pd manual. I have observed that when the setup is good i.e. TX PRBS pattern is initiated as per the (A), I can see the counter changing for all the lanes which are active and transmitting PRBS. Can you please let me know what is that counter mean?

PHY-A, 2 Lane (B4) à 0x02325FF8  (page 67 of the manual sub-system WIZ offset add: 0x1FF8)

PHY-A, 4 Lanes (B8) à 0x02327FF8  (page 71 of the manual sub-system WIZ offset add: 0x1FF8)

Looking forward to hear from you. Thanks

Kind Regards

Nitish

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UC3825B: UC3825B

February 4, 2019, 3:40 am
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Part Number:UC3825B

Dear Sir/Madam,

 

Greeting from Micropower!!!

               

We are happy to introduce ourselves as a leading manufacturer of SMPS brand “Micro Power” catering to various industrial applications in “Electronics and Surveillance” and “Industrial Automation”.

Please visit our website  www.micropower-india.com

 

We are developing one new product for which we have used TI make UC3825BN PWM controller

 

But we are facing problem in problem with PWM controller.

Actually PWM controller not even started.

We did not got VCC at PWM, it will drop the internal start up VCC given by start up resistors.

We have then gave external VCC then PWM controller started but then also we didn't got the voltage value at soft start pin. no 8.

So can you please guide us in proper way.

Thanks & Regards,

Aniket Band

Head, R & D Department,

Sanstar Microsystems Pvt. Ltd.

EL-15, Electronics Zone,

M.I.D.C Hingna Road,

Nagpur-440016

+91 96079 70446 / +91 80078 77425

Web: www.micropower-india.com

 

An ISO 9001:2015 certified company!

 

 

 

 

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Electromechanical audio transducer driver

February 4, 2019, 3:42 am
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Can we connect Electromechanical audio transducer to audio amplifier.

The specification of the transducer is 

RATED VOLTAGE                              12 Vpk
OPERATING VOLTAGE RANGE        8 ~ 14 Vpk
RATED CURRENT (MAX)                  55 mA
COIL RESISTANCE                           120 OHM
MINIMUM SPL @ 10 CM (@ 1kHz)   85 dBA
RESONANT FREQUENCY                1,000 - 1,500 Hz

We have connected 3.3V/5V to supply voltage of the IC

I am looking for an audio amplifier that can drive this audio transducer.

Thanks

regards

Subramani

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TMS320F28379D: C2000Ware driverlib IPC

February 4, 2019, 3:43 am
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Part Number:TMS320F28379D

Hi,

Is there any IPC module or set of APIs within driverlib? I haven't found it. I have only found them under bit-field folder. I want to avoid, as far as possible, using bit-field files.

Is there anything I can use within driverlib?

Best regards,

Adria

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DK-TM4C123G: DK-TM4C123G development kit Revision

February 4, 2019, 3:46 am
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Part Number:DK-TM4C123G

Hi Team

 

I have DK-TM4C123G Rev A0.

Is it the latest version? I couldn’t find the information for it.

Is there any limitation to use this?

 

Thanks and Best regards,

Kuerbis

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Linux/WL1835MOD: MIMO mode Antenna 2 Not working

February 4, 2019, 3:50 am
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Part Number:WL1835MOD

Tool/software: Linux

Hi,

Issue1:

We are having difficulty  in getting 2.4 GHz MIMO working with WL1835MOD as AP in Antenna 2.We are not even seeing any transmission on Antenna 2.

We Hardware disabled Antenna 1 to validate our observation.  

In wl18xx-conf.bin we have set:

wl18xx.ht.mode=0x0

wl18xx.phy.number_of_assembled_ant2_4=0x02

Issue2:

In PLT mode when we set Antenna value 3 in calibrator set_tx_power command we are seeing  transmissions happening in only one Antenna.

Is there any other configuration required to set?  

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Compiler/TMS320TCI6618: C66 MSMC non Cache read cycles penalty

February 4, 2019, 3:52 am
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Part Number:TMS320TCI6618

Tool/software: TI C/C++ Compiler

Hi,

I am accessing MSMC non cached memory. According to document sprabh2a.pdf ,  MSMC non cached memory is having penalty of 12 cycles.

Since I am accessing data 139 *256 bits(_mem8_const) , I am seeing penalty of 9000 cycles instead of 6672 cycles[12 * 4 * 139 according to sprabh2a.pdf]

Please find the code below:

tPayload -- > Pointing to MSMC non cached memory
tempData -- > Pointing to L2_ISRAM

Header = TimeStampTable[hdrCount];

#pragma MUST_ITERATE(1,139,1);
for(loopCount = 0; loopCount < pairLoop; ++loopCount)
{

Value1 = _mem8_const(tPayload++);
Value2 = _mem8_const(tPayload++);
Value3 = _mem8_const(tPayload++);
Value4 = _mem8_const(tPayload++);

#if 1
hdrFlag = ( _cmpeq4(_loll(Value1), 0) &
_cmpeq4(_hill(Value1), 0) &
_cmpeq4(_loll(Value2), 0) &
_cmpeq4((_hill(Value2) & MASK), Header));
#else
hdrFlag = ( _cmpeq4(_hill(Value1), 0) &
_cmpeq4(_loll(Value1), 0) &
_cmpeq4(_hill(Value2), 0) &
_cmpeq4((_loll(Value2) & MASK), Header));
#endif

if(hdrFlag == 15)
{
hdrCount++;

*tempData++ = Value3;
*tempData++ = Value4;

temp = _cmpeq2(hdrCount, 0xffff005f) - 1;
hdrCount = hdrCount & temp;
countData++;
Header = TimeStampTable[hdrCount];
}
}

Please help in understanding why 3000 cycles are taken extra and also help in mitigating the issue.

Note: Above loop takes only 3300 cycles when both tempData and tPayload are in L2_ISRAM memory.

Regards 

Shreyas N

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TMDSEMU110-U: How to use this driver in CCF uniflash to debug TMS320F28377D controller

February 4, 2019, 3:55 am
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Part Number:TMDSEMU110-U

Recently we bought TMDSEMU110-U to debug TMS320F28377DZWT DSP. But we dont have driver to debug the same using CCF uniflash.

Can anyone help me to find the driver for debugging this DSP using cc uniflash.

Image of usb device showing in device manager while connecting specified part no:TMDSEMU110-U attcahed

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MSP430FR2522: MSP430FR2522

February 4, 2019, 3:59 am
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Part Number:MSP430FR2522

Hello sir,We are working on captivate single touch keypad.I don't have awareness of msp controller.could you please provide any related documents,libraries for keypad configuration using serial communication(I2C,UART).

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TINA/Spice/OPA838: The OPA838 TINA spice model has occurred floating error for using some standard SPICE.

February 4, 2019, 4:02 am
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Part Number:OPA838

Tool/software:TINA-TI or Spice Models

I tried to use the OPA838 with LTspice :-P,  however the TINA SPICE model has occrred a floating error at GRA and GRC node.

I have solved this error to modify as below,

* Modified for LTspice by Akihiro Kawata with Fukuda Denshi, Feb/4.2019
* Need to add RA for preventing floating error.
*GRA 101 102 VALUE = {V(101,102)/1e6}
GRA 101 102 101 102 1e-6
RA  102 GNDF 1e12

CA  102 GNDF 1e3

* Modified for LTspice by Akihiro Kawata with Fukuda Denshi, Feb/4.2019
* Need to add RC for preventing floating error.
*GRC 301 302 VALUE = {V(301,302)/1e6}
GRC 301 302 301 302 1e-6
RC  302 GNDF 1e12

CC  302 GNDF 1e3

Node 102 and 303 are connected to CA or CC, it is ideal capacitor, therefore I think some SPICE simulator has occrred the floating node error.

I hope this issue to be corrected by TI.

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CCS/LAUNCHXL-CC1350: cc1350

February 4, 2019, 4:06 am
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Part Number:LAUNCHXL-CC1350

Tool/software: Code Composer Studio

i made changes in config file and uploaded bin file in smart rf

but am getting error like device is not in boot loader mode

may i know where am missing

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