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EVMK2H: Password for the GIT repo for Keystone II Boot Examples

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Part Number:EVMK2H

Hi there,

I'm trying to get boot examples for the Keystone II, and as per the wiki (linked here) it says to clone the GIT repo. I entered the command as directed in my git bash environment and it prompted me for a password: 

Nowhere on the wiki do I see any mention of a password. Could I please be provided with a password in order to continue with the boot examples?

Thanks.


CCS/LAUNCHXL-F28379D: Problems implementing a Phase Locked Loop Algorithm using ADC

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Part Number:LAUNCHXL-F28379D

Tool/software: Code Composer Studio

Hello, I'm new using the C2000 family of microcontrollers and having troubles to implementing a Single Phase Phase Locked Loop algorithm in my F28379D DSP.

The signal I'm tracking is a sine wave created by EPwm5 varrying it's that Duty Cycle with EPwm5Regs.CMPA.bit.CMPA register. Then I connect the output of the Epwm5A on low-pass filter and read with ADC0 pin the filtered signal and gets this:

Then I have to treat digitally the wave to become a sine wave varrying from 1 to -1. Here starts my doubts.

I created a static float variable to try to reach this signal but it's value keeps on 0. After this I'll need to implement the difference equation using the values of the new variable digitally treated. Below it's the code that I tried to use in the void of the ADC routine.

#define ajuste_tensao 1/1864
#define offset 1800.0

static float seno_entrada;

interrupt void adca1_isr(void){

AdcaResults[resultsIndex++] = AdcaResultRegs.ADCRESULT0;
seno_entrada = ((AdcaResults[1])-offset)*ajuste_tensao;
if(RESULTS_BUFFER_SIZE <= resultsIndex)
{
resultsIndex = 0;
bufferFull = 1;
}

AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

if (n<6.283){
n=n+ajuste;
sen=0.5*(1+sin(n));
EPwm5Regs.CMPA.bit.CMPA = sen*0x1000;
}
else{
EPwm5Regs.CMPA.bit.CMPA = 0x0000;
n=0;
}

}

TMS320F28377S: Trouble with Power-Up Sequence

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Part Number:TMS320F28377S

Hi,

I am using the TMS320F28377S MCU on a custom board. When powering up the board, there are times where the board goes into an undefined state. When this happens we just reset the board using a switch tied to the XRS pin. This does not happen every time we power-up, some times we power up with no problem. Currently we have a RC circuit attached to the XRS pin as described in Section 5.9.2 of the data sheet. 

In order to fix this we are looking to add a voltage supervisor circuit to monitor the 3.3V rail and/or the 1.2V rail during power-up. To help, I am looking for the following information:

-The 3.3V rail voltage and 1.2V rail voltage where the Power on reset releases the XRS pin

-The 3.3V and 1.2V brown out voltages, per the datasheet, section 5.4, the recommended operating 3.3 rail min is 3.14V and the 1.2 rail min is 1.14V. However, brown-out voltage is not listed.

-Any recommendation on a voltage supervisor with 100mV or more of hysteresis.

Thank you.

Best,

Jeremy Bower

DAC161S997EVM: Firmware

CCS/TMS320F28027: CCS/TMS320F28027

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Part Number:TMS320F28027

Tool/software: Code Composer Studio

Hi! I am new with C2000 family and Code composer programming. I was trying to debug one of the available examples of f28027 on RAM. I got the error message when I tried to build, only after filling the Linker command file field with 2802_RAM_lnk.cmd instead of F2802x_Headers_nonBIOS.cmd. The error report in the console was showed: "RAMM1 memory range overlaps existing memory range RAMM1".

I don't know why because I didn't change anything in the program. Does anyone else had the same problem as me, and so, how did you solve it?

I appreciate any help. Have a nice day!

PCM5242: Additional charge pump load

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Part Number:PCM5242

Hi, Can I get few mA of current from Vneg pin PCM5242 to supply 2 operational amplifiers?

ADS1298: Lead resistance effect ; Noise ; CMRR

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Part Number:ADS1298

Hi,

We are designing custom ECG electrode with flexible printed wires as to reduce wires clutter from different electrode. The manufacturer has made the patch but the resistance variation between all the three electrode varies, which is 20 ohm, 5 ohm and 30 ohm respectively.

Is this variation acceptable or resistance of the electrode and the the lead as seen by the amplifier should be same. Considering the electrode-skin interface in which variation is in the order of 1000 of ohm, is variation of lead resistance by 15 to 50 ohm acceptable. If we consider common mode noise variation across leads with different resistance, will amplifier amplify common mode noise, thus amplifying noise.

Does the TI's ADS1298 provide all the required signal conditioner to off-set the variation in the lead resistance.  Will using the right leg drive can help to reduce the noise? How should be move forward in spite of unequal resistance in the signal path or it will have negligible effect.

Regards,

Tapas

RTOS/PROCESSOR-SDK-AM57X: Add custom Layer 2 ethertype as custom socket in TI-RTOS SDK 05.01.00.11

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Part Number:PROCESSOR-SDK-AM57X

Tool/software: TI-RTOS

Hello,

I'm using AM572x IDK board with TI-RTOS SDK 05.01.00.11.

I want to use standard socket API for send/receive packages (GOOSE and SV). I require UDP-like transport (datagrams).

And I also need to support sending and receiving it over VLANs, like usual TCP or UDP packets.

I already asked support about VLANs: https://e2e.ti.com/support/processors/f/791/p/758084/2814479#2814479, but their answer was not correct for me, as I understand: I need to send and receive messages with different length.

Tell me, please, how can I add custom ethertype (GOOSE and SV) for VLAN and default socket API support?

With regards,
Alex


BQ34110: How the error on the Thermistor translate in temperature

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Part Number:BQ34110

Hi,

We are looking for the temperature error depending on the thermistor tolerance. In example, if we have a thermistor value that is X ohm above the theoretical value, how the temperature is affected.

BQ34110: I2C timeout

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Part Number:BQ34110

Hi,

We have a rare occurrence of I2C timeout and we have a timeout set at 10ms for a 100kHz I2C. We don't find any limitation in the datasheet on the I2C. Is there any other document that could put constrain on the I2C like delays between commands and things like that.

Note: Before we had a timeout at 1ms and we were getting that error from time tot time. But since we have put the 10ms it become very reliable, but not perfect.

TDA3XEVM: How are bit map arrays generated?

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Part Number:TDA3XEVM

Graphics source link contains number of bitmap arrays. 

For example, filename draw2d_ti_logo_white.c contains array gDraw2D_Bmp

How is this  array created?  Was the logo created in some image editing program like Adobe Photoshop and saved as file type bitmap.  Then, what program was used to convert bitmap file to 'C' language array?

Is this the process I follow to create custom images?

Regards,

Amer

TLV320ADC3101: What can ADC3101's miniDSP do by TI embedded algorithm?

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Part Number:TLV320ADC3101

Hi Team,

Could you help to list a simple functions list that ADC3101's miniDSP can do by TI embedded algorithm?

Customer are curious about the miniDSP benefit.

Thanks

CCS/TMS320F28027F: CCS/TMS320F28027F: Question about locked device

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Part Number:TMS320F28027F

Tool/software: Code Composer Studio

Hello,

I can not connect and I receive the following error:

Error connecting to the target:
(Error -1015 @ 0x0)
Device is not responding to the request. Device may be locked, or the debug probe connection may be unreliable. Unlock the device if possible (e.g. use wait in reset mode, and power-cycle the board). If error persists, confirm configuration and/or try more reliable JTAG settings (e.g. lower TCLK).
(Emulation package 8.0.903.2)

I have looked into multiple threads on TI forum and checked things as listed :

1. The controller did not experience any power failure while flashing the code

2. The JTAG integrity test has succeeded.

What steps do I follow to unlock the device or to wait in the reset mode ? Do I have to alter something in the code or do I have change any configuration on Code Composer Studio?

Thanks,

Anushka

CC2640R2F: Which Event from the Stack to be used to identify a new connection with a trusted Master just started

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Part Number:CC2640R2F

Hello Champions,

on a Multirole project I'm following based on SDK 1.35.00.33 , Multirole-Peripheral role  can be connected from a smartphone behaving as Master .

By default , Multirole project requires a 6 digits PIN  . When then PIN is issued by the Master for the first time, I can trace Bonding events on multi_role_processPairState().

When pairing-authentication and bonding are done, next time the smartphone tries to connect, a  PIN is no more required as expected .

In this last situation, I'm not able to trace any events to be informed the connection is enstablished and trusted .

My question for you : Which Event from the Stack I can use to be aware that a connection with a bonded Master just happened ?

Thank you,

Paolo

SN65LVDS100: power dissipation

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Part Number:SN65LVDS100

Dear Team,

Can you please advise what is the difference (meaning) between power dissipation rating (described on the datasheet on table 8.4 - p.5) and device power dissipation on table 8.5 (same page).

Best regards,

Nir.


CCS/LAUNCHXL2-570LC43: error 260@0x0

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Part Number:LAUNCHXL2-570LC43

Tool/software: Code Composer Studio

Sir, 

I have created my own custom board using the schematic of LAUNCHXL2-570LC43. but unable to connect it to CCSV7.3. its showing error code 260@0x0, emulatiom package 7.0.48.0. i am using the debug probe that is provided with LAUNCHXL2-570LC43 evaluation board. kindly help. the debug probe is working fine with evaluation boatrd.

kindly help

Regards,

Deepak

AM5728: SDK: LINUX-RT vs TI-RTOS on Linux

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Part Number:AM5728

Hi,

We are considering using a Linux environment for our development. We currently are using TI-RTOS on Windows 10. We want to use various peripherals and network capabilities in a hard real-time system.

My questions are:

  1. What's the difference between the SDK for Linux-RT and the SDK for TI-RTOS on Linux?
  2. What's the difference between TI-RTOS on Windows and TI-RTOS on Linux?
  3. Are there any added benefits from choosing one over the other? 

Thanks in advance.

Alec

CCS/RM48L952: Flash ECC Errors when compiling with TI 18.4.1 LTS compiler, not present with 16.9.x compiler versions

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Part Number:RM48L952

Tool/software: Code Composer Studio

I raised this issue previously on another thread

Upon installing the latest CCS v8.x to a new laptop and rebuilding my application from CCS v7.x I started to get Flash ECC errors whenever I wrote to a RAM variable through the debug server interface. This only occurs when I build with the latest compiler that ships with v8.x; install and specify the earlier CCS v7.x packaged compilers and my application runs OK. We are at production release so I will continue to just use the earlier compiler. But in parallel I need to identify the root cause.

Previous version was TI 16.9.0 LTS, I installed 16.9.10 and it works well. Version 18.1.4 throws the Flash ECC errors.

Thanks in advance for paths to identifying root cause. Any known differences in the compiler would be of interest. 

LAUNCHXL-F28379D: eCap Delta Timing

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Part Number:LAUNCHXL-F28379D

I'd like to use the eCap in delta mode to capture time stamps with rising and falling edge detection as described in http://www.ti.com/lit/ug/sprug79/sprug79.pdf

   //
    // Disable ,clear all capture flags and interrupts
    //
    ECAP_disableInterrupt(ECAP1_BASE,
                          (ECAP_ISR_SOURCE_CAPTURE_EVENT_1  |
                           ECAP_ISR_SOURCE_CAPTURE_EVENT_2  |
                           ECAP_ISR_SOURCE_CAPTURE_EVENT_3  |
                           ECAP_ISR_SOURCE_CAPTURE_EVENT_4  |
                           ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                           ECAP_ISR_SOURCE_COUNTER_PERIOD   |
                           ECAP_ISR_SOURCE_COUNTER_COMPARE));
    ECAP_clearInterrupt(ECAP1_BASE,
                        (ECAP_ISR_SOURCE_CAPTURE_EVENT_1  |
                         ECAP_ISR_SOURCE_CAPTURE_EVENT_2  |
                         ECAP_ISR_SOURCE_CAPTURE_EVENT_3  |
                         ECAP_ISR_SOURCE_CAPTURE_EVENT_4  |
                         ECAP_ISR_SOURCE_COUNTER_OVERFLOW |
                         ECAP_ISR_SOURCE_COUNTER_PERIOD   |
                         ECAP_ISR_SOURCE_COUNTER_COMPARE));


//    ECap1Regs.ECCTL1.bit.CAP1POL = ECAP_EVNT_RISING_EDGE;
//    ECap1Regs.ECCTL1.bit.CAP2POL = ECAP_EVNT_RISING_EDGE;
//    ECap1Regs.ECCTL1.bit.CAP3POL = ECAP_EVNT_RISING_EDGE;
//    ECap1Regs.ECCTL1.bit.CAP4POL = ECAP_EVNT_RISING_EDGE;

    ECAP_setEventPolarity(ECAP1_BASE, ECAP_EVENT_1, ECAP_EVNT_RISING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE, ECAP_EVENT_2, ECAP_EVNT_FALLING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE, ECAP_EVENT_3, ECAP_EVNT_RISING_EDGE);
    ECAP_setEventPolarity(ECAP1_BASE, ECAP_EVENT_4, ECAP_EVNT_FALLING_EDGE);

//    ECap1Regs.ECCTL1.bit.CTRRST1 = 1; // Difference mode
//    ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // Difference mode
//    ECap1Regs.ECCTL1.bit.CTRRST3 = 1; // Difference mode
//    ECap1Regs.ECCTL1.bit.CTRRST4 = 1; // Difference mode
    ECAP_disableCounterResetOnEvent(ECAP1_BASE, ECAP_EVENT_1);
    ECAP_disableCounterResetOnEvent(ECAP1_BASE, ECAP_EVENT_2);
    ECAP_disableCounterResetOnEvent(ECAP1_BASE, ECAP_EVENT_3);
    ECAP_disableCounterResetOnEvent(ECAP1_BASE, ECAP_EVENT_4);

//    ECap1Regs.ECCTL1.bit.CAPLDEN = 1;
    ECAP_enableTimeStampCapture(ECAP1_BASE);

//    ECap1Regs.ECCTL1.bit.PRESCALE = 0;
    ECAP_setEventPrescaler(ECAP1_BASE, 1);

//    ECap1Regs.ECCTL2.bit.CAP_APWM = 0;
    ECAP_enableCaptureMode(ECAP1_BASE);

//    ECap1Regs.ECCTL2.bit.CONT_ONESHT = 0;
    ECAP_setCaptureMode(ECAP1_BASE, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_1);
    ECAP_setCaptureMode(ECAP1_BASE, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_2);
    ECAP_setCaptureMode(ECAP1_BASE, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_3);
    ECAP_setCaptureMode(ECAP1_BASE, ECAP_CONTINUOUS_CAPTURE_MODE, ECAP_EVENT_4);

//    ECap1Regs.ECCTL2.bit.SYNCO_SEL =  2;
    ECAP_setSyncOutMode(ECAP1_BASE, ECAP_SYNC_OUT_DISABLED);

//    ECap1Regs.ECCTL2.bit.SYNCI_EN =   0;
    ECAP_disableLoadCounter(ECAP1_BASE);

    XBAR_setInputPin(XBAR_INPUT7, 16);

//    ECap1Regs.ECCTL2.bit.TSCTRSTOP =  1;
    ECAP_startCounter(ECAP1_BASE);

    ECAP_enableInterrupt(ECAP1_BASE, ECAP_ISR_SOURCE_CAPTURE_EVENT_1);

//    cap4Count = ECap1Regs.CAP4;
//    cap1Count = ECap1Regs.CAP1;
//    cap2Count = ECap1Regs.CAP2;
//    cap3Count = ECap1Regs.CAP3;
    DutyOnTime1 = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_2);
    DutyOffTime1 = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_3);
    DutyOnTime2 = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_4);
    DutyOffTime2 = ECAP_getEventTimeStamp(ECAP1_BASE, ECAP_EVENT_1);

    Period1 = DutyOnTime1 + DutyOffTime1;
    Period2 = DutyOnTime2 + DutyOffTime2;

    ecap1IntCount++;

    //
    // Clear interrupt flags for more interrupts.
    //
    ECAP_clearInterrupt(ECAP1_BASE,ECAP_ISR_SOURCE_CAPTURE_EVENT_1);
    ECAP_clearGlobalInterrupt(ECAP1_BASE);

    //
    // Acknowledge the group interrupt for more interrupts.
    //
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP4);

Thanks!

TMS320F28379D: While changing ePWM period and duty on the fly, output is not continuos.

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Part Number:TMS320F28379D

Hi dear people!
Progressing in my application, I am in need of a variable output in one ePWM channel,
changing Period and Duty every millisecond.

If I do this inside a loop, the ePWM get periods of time (around 1,3 mS) where the output is zero. The pin goes down for 1,3 mS, and then the normal operation continues.

Those "black-outs" correspond to the end of the setting with the largest Period, it fails to change to the quicker setting.

Sometimes, however, it succeed, ramdonly.

I include some screenshots to show this.
In the screenshots I use a DELAY_US(500); to toggle a pin to make things more clear to you. 
Every time the pin toggles, the settings should change too.

I have changed the settings and changed the time every setting is active, without succes.
The 1,3 mS periods occur at different intervals, but always by the end of the period with the slower setting.
I have used another Launchpad.
Running the Launchpad in stand alone, without my custom circuit, does not help either.
If I run the loop with only one of the settings, everything is fine.
I have stoped the ePWM with
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
before making the changes and started it again, no changes.

If I use a slider to modity those setings, everything is fine, but if I run it in a loop not.

Is there a way to do this?

Below I include the two settings and the configuration of the ePWM

Thanks in advance for your opinion!

Greetings from Germany,

Gustavo

EPwm4Regs.TBPRD = 176;
EPwm4Regs.CMPA.bit.CMPA = 107;
EPwm4Regs.CMPB.bit.CMPB = 107;

EPwm4Regs.TBPRD = 57;
EPwm4Regs.CMPA.bit.CMPA = 35;
EPwm4Regs.CMPB.bit.CMPB = 35

void HRPWM4_Config(period)

{
EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE;
EPwm4Regs.TBPRD = 176;
EPwm4Regs.CMPA.bit.CMPA = 107;
EPwm4Regs.CMPA.bit.CMPAHR = (0 << 8);

EPwm4Regs.CMPB.bit.CMPB = 107;
EPwm4Regs.CMPB.all |= (0 << 8);


EPwm4Regs.TBPHS.all = 0;
EPwm4Regs.TBCTR = 0;

EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;

EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;

EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;
EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EPwm4Regs.ETSEL.bit.INTEN = 1;

EPwm4Regs.ETPS.bit.INTPSSEL = 0x0;
EPwm4Regs.ETPS.bit.INTPRD = 0x0;
EPwm4Regs.ETSEL.bit.INTSELCMP = 0x0;
EPwm4Regs.ETSEL.bit.INTSEL = 0x6;

EALLOW;
EPwm4Regs.HRCNFG.all = 0x0;
EPwm4Regs.HRCNFG.bit.EDGMODE = HR_FEP;
EPwm4Regs.HRCNFG.bit.CTLMODE = HR_CMP;
EPwm4Regs.HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
EPwm4Regs.HRCNFG.bit.EDGMODEB = HR_FEP;
EPwm4Regs.HRCNFG.bit.CTLMODEB = HR_CMP;
EPwm4Regs.HRCNFG.bit.HRLOADB = HR_CTR_ZERO;
EDIS;
}

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