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CC3220S-LAUNCHXL: How to do SPI communication with MSP430?

January 16, 2019, 6:07 pm
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Part Number:CC3220S-LAUNCHXL

Hi,

I am trying out the TI driver SPI Master example from the CC3220S sdk. I am trying to communicate with the MSP430FR4133 which uses the TI MSPWare SPI slave example. How do I match the SPI settings correctly?

CC3220S code

    /* Open SPI as master (default) */
    SPI_Params_init(&spiParams);
    spiParams.frameFormat = SPI_POL0_PHA0;
    masterSpi = SPI_open(Board_SPI_MASTER, &spiParams);

MSP430FR4133 code

    //Initialize slave to MSB first, inactive high clock polarity and 3 wire SPI
    EUSCI_B_SPI_initSlaveParam param = {0};
    param.msbFirst = EUSCI_B_SPI_MSB_FIRST;
    param.clockPhase = EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT;
    param.clockPolarity = EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW;
    param.spiMode = EUSCI_B_SPI_3PIN;
    EUSCI_B_SPI_initSlave(EUSCI_B0_BASE, &param);

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TPS546C23: Please check the schematic design

January 16, 2019, 6:13 pm
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Part Number:TPS546C23

Hi all

    I'm using TPS546C23 chip in my project. Please check the schematic design. Thank you for your help

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what resolution of camera I can use with this part?

January 16, 2019, 6:15 pm
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wondering what is the max data  size

Datasheet is saying as 4MP @30fps or 2MP @30fps as below

"4.16-Gbps Grade Serializer Supports High-Speed Sensors Including Full HD 1080p 2MP 60-fps and
4MP 30-fps Imagers"

Any confirmation would be appreciate to use size of image data transmit. 

Regards Vrai

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CCS: tms5704357 canfd test rx question

January 16, 2019, 6:20 pm
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Tool/software: Code Composer Studio

Hello. I'm working on a project right now.
I am currently working on a project to test the TCAN4550-Q1 using the TMS570LC4X.
One of the two boards is TX and the other board is RX. One of them is TX CODE and the other is RX.

But there's a problem here, and I'm going to contact you.
I'll talk about this.

Receiving a signal at rx when it is continuously transmitting at tx, the signal at tx stops, and rx receives the signal and transmits it to spi, confirming that it enters the corresponding rx buffer. No, the signal does not go in at once. I have to do it several times. When receiving the rx signal from the tx signal, it is necessary to send the recognized signal by confirming that rx has been received.

What I did when I sent the signal on rx basis.
Please review once.

I wonder if I need to take another action to get the rx signal.
I want to know how the signal is constant.
I will put the contents and the pictures I have together.

Please teach me a lot.

RegisterAddressActionValueNOTES
Device
Interrupts		0x0820READ0x80000082M_CAN_INT bit is set, so MCAN has an interrupt
IR0x1050READ0x00000010New message in RX FIFO 1, need to read RX FIFO 1 status to get more information
IR0x1050WRITE0x00000010Clear the interrupt by writing the bit back to the IR register
RXF0S0x10A4READ0x00040301There is 1 unread message in the FIFO at index 3
-0X81C8--Based on setup in Table 7, start address for index 3 is: hex(72 * 3) +0x80F0 = 0x81C8
RX FIFO0[3]0x81C8READ0x52345678Header word #1, XTD is set and ID[28:0] = 0x12345678
RX FIFO0[3]0x81CCREAD0x01B70000Header word #2, 7 bytes of data sent with CAN FD and BRS enabled
RX FIFO0[3]0x81D0READ0x44332211First 4 bytes of data, 0x11 is the first received byte
RX FIFO0[3]0X81D4READ0x00776655Last 3 bytes of data, 0x77 was the last received byte
RXF0A0X10B8WRITE0x00000003Write the index of the FIFO index read to acknowledge that it has
been read and clear it for use

* read write spi 

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DP83620: The default configuration

January 16, 2019, 6:26 pm
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Part Number:DP83620

I am looking at the MDIO/MDC interface to program the registers from FPGA, but the interface core is not ready yet.

wondering if no register configuration can work for 100BaseTX as default ? Firstly, try to work with TXCLK, TXEN, TXD[3:0] data between FPGA and DP83620 .

Will it work without an configuration through MDIO/MDC ?

the MAC Controller will send 32bit data format.. is there any data bit ordering to 4bit MII data format for DP83620?

Regards vrai

 

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TPS53513: Please check the schematic design

January 16, 2019, 6:28 pm
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Part Number:TPS53513

Hi All

   I'm using TPS53513 chip in my project . Please check the schematic design. Thank you for your help

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TPA3138D2: TPA3138D2

January 16, 2019, 6:36 pm
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TPS54424: Please check the schematic design

January 16, 2019, 6:43 pm
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Part Number:TPS54424

Hi all

I'm using this TPS54424 chip. Please check the schematic design. Thank you for your help

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DS250DF210: DS250DF210 Programming Guide(SNLU202)

January 16, 2019, 6:53 pm
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CC1352P: Is there any side effect if I disable "valid header" checking

January 16, 2019, 6:55 pm
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Part Number:CC1352P

Hi all,

I try to add OTA function on our own board but we always get "OTA abort" when start. In debug mode, the system hit "return ZCL_STATUS_ABORT" in zcl_ota.c --> zclOTA_ProcessImageData() --> case OAD_GET_IMAGE_HDR_STATE: -->

//is a valid header
if(memcmp(&oad_imgHdrFactoryNew.fixedHdr.imgID, oad_externalFLashID, sizeof(oad_externalFLashID)) != 0)
{
flash_close();
//This release does not support not having the Factory New image
return ZCL_STATUS_ABORT;
}

If I disable this checking, the OTA can work correctly. My question is : Can I ignore this checking? Thanks

SW : simplelink_cc13x2_sdk_2_30_00_45

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TINA/Spice/TINA-TI: a Electrical device library that is neither TINA_TI library nor Spice library

January 16, 2019, 6:55 pm
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Part Number:TINA-TI

Tool/software:TINA-TI or Spice Models

l read TINA_TI manuals.

But there is no explanation for a Electrical device library that is neither TINA_TI library nor Spice library.

I want to use CDBB2100-G for simulation.

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TLV320AIC3104: I cannot install AIC3104 GUI

January 16, 2019, 7:00 pm
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Part Number:TLV320AIC3104

Hi,

When I double clicked setup.exe, it pop a window that The windows installer engine is corrupt,. To attempt to resolve this issue, please register the engine by regsvr32.exe on msi.dll.

I don't know how to run msi.dll, could you please help me? I looked for the answer in the e2e, looks like other people didn't meet this issue before. My OS is WIN10. 

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RTOS/AWR1642: AWR1642 - FLT_EPSILON

January 16, 2019, 7:07 pm
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Part Number:AWR1642

Tool/software: TI-RTOS

Hi,

May I know the FLT_EPSILON value of AWR1642 or C674x?

Thank you

Chee Peng

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Compiler/AM5728: Random error compiling source code for the C66 on Sitara for no apparent reasons.

January 16, 2019, 7:15 pm
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Part Number:AM5728

Tool/software: TI C/C++ Compiler

Hi, 

I am having a similar problem where our DSP Code would randomly give errors for no apparent reason. Rebuilding resolves the problem but it make us waste a lot of time as it happen more and more frequently and we have to restart our release build in order to get it right. 

Here is the type of errors that we see. 

Compilation triggered by a bitbake recipe

Building file: /releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/common/ipc/ipcserver.c
| Invoking: C6000 Compiler
| "/opt/ti-rtos/am57xx/2.0/ti-cgt-c6000_8.1.3/bin/cl6x" -mv6600 -O3 --opt_for_speed=5 --include_path="/opt/ti-rtos/am57xx/2.0/ti-cgt-c6000_8.1.3/include" --include_path="/opt/ti-rtos/am57xx/2.0/mathlib_c66x_3_1_1_0/packages" --include_path="/opt/ti-rtos/am57xx/2.0/dsplib_c66x_3_4_0_0/packages" --include_path="/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/jupiter/common" --include_path="/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/host/mrdspaccess/inc" --include_path="/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/mrdspapp/src/include" --include_path="/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/mrdspapp/src/ti/opus" --include_path="/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/mrdspapp/src/ti/g722" --define=am5726 --define=IVCNEXTGEN --define=SOC_AM572x --define=VAYU_DSP_1 --define=core1 --diag_wrap=off --diag_warning=225 --emit_warnings_as_errors --display_error_number --gen_func_subsections=on --no_bad_aliases --debug_software_pipeline --fp_mode=relaxed --preproc_with_compile --preproc_dependency="ipc-common/ipc/ipcserver.d" --obj_directory="ipc-common/ipc" --cmd_file="configPkg/compiler.opt" "/releases/neptune/NEP-1.16.0.0/common.hg/yocto/ti/build/arago-tmp-external-linaro-toolchain/work/armv7ahf-neon-clearcom-linux-gnueabi/ivcdsp/0.0.1-r2.1/dsp.hg/common/ipc/ipcserver.c"

Get this

"ipcserver.asm", ERROR!   at line 30: [W0003] This file contains DWARF
|                                               directives that can only be used
|                                               in unmodified assembly files
|                                               generated by the compiler;
|                                               ignoring all DWARF directives
| 	$C$DW$CU	.dwtag  DW_TAG_compile_unit
| 
| "ipcserver.asm", ERROR!   at line 355: [E0003] Unexpected trailing operand(s)
| 		.sect	".resource_table", RW
| 
| "ipcserver.asm", ERROR!   at line 1111: [E0900] Common symbols require ELF
|                                                 object format
| 		.nearcommon	dspRegisters,4,4
|

...

INTERNAL ERROR: /opt/ti-rtos/am57xx/2.0/ti-cgt-c6000_8.1.3/bin/asm6x experienced a segmentation fault
|                   while processing section .text:jupiter_user_task file ipcserver.asm line 1263
| 
| This is caused by a defect in the compiler itself. TI Customer
| Support may be able to suggest a workaround to avoid this.
| 
| Upgrading to the newest version of the compiler may fix this problem.
|

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TPS22910A: load switch transition

January 16, 2019, 7:16 pm
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Part Number:TPS22910A

Hi,

I'm planning to use TPS22910A and TPS22913B load switch for one of my battery operated circuit.

The switch is  just used to connect battery output to a resistor divider network ( battery ---TPS22910A/TPS22913B----- Resistor divider). Switch is enabled by Microcontroller GPIO.

1. Do I need to still connect an output capacitor ( C load) ?

2. Data sheet says output capacitor as optional. What is the significance of the same ?

3. What slew rate will be the switch working with no output capacitor connected ?

4. My load current is only 12-15 Micro amperes.

Thanks

Anil

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RTOS/TMDSOSKL137: [evmOMAPL137]For recording reading data(mic in and line in), which parts or variables that I should see and modify?(MCASP_Audio_evmOMAPL137_c674xExampleProject)

January 16, 2019, 7:31 pm
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Part Number:TMDSOSKL137

Tool/software: TI-RTOS

Hello,

My evm is TMDSOSKL137, I'm using Processor SDK RTOS 05_02_00_10

and I 'm testing pdk example 

C:\ti\pdk_omapl137_1_0_7\packages\MyExampleProjects\MCASP_Audio_evmOMAPL137_c674xExampleProject

For recording reading data(mic in and line in),  which parts or variables that I should see and modify?

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ADS131E08: ADS131E08 CS pin

January 16, 2019, 7:34 pm
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Part Number:ADS131E08

DSP connectedwith ADS131E08 by SPI,  DSP can not  communicate with ADS131E08 as the CS pin connect to GND by 4.7K resistance, but when use a DSP IO to control the ADC, it's OK. Why?

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UCC28950: UCC28950 miss TON pulse at start up within light load

January 16, 2019, 7:34 pm
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Part Number:UCC28950

Hi Expert,

Pls help us to know why UCC28950 miss TON pulse at start up within light load.

Below is the measurements on UCC28950 pin directly from the customer board.

Picture 1 (OUTB is missing for 356uS) 

Picture 2  (SS/EN and COMP is ramping up now)

 

Pls advice.

Best regards,

Eric Lai

 

Field Application Engineer

Texas Instruments Taiwan Limited

O: +886-2-2175-2582

M: +886-909-262-582

E-Mail:Eric.Lai@ti.com 

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TPS7A85: Required ECCN details

January 16, 2019, 7:47 pm
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Part Number:TPS7A85

Dear sir/Madam,

             Please provide the Export classification(ECCN) details of  TPS7A8500RGRT.

Thanks and Regards,

KARTHI P

Indus Teqsite(India) private limited

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CCS: I know that the file mmWaveLink is the interface file, So what is the amplitude, frequency and phase of a FMCW signal?

January 16, 2019, 7:52 pm
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Tool/software: Code Composer Studio

For example, there's bound to be an error in the transformation between the analog value and the digital value, So in the figure below, what is the error value generated by each device?I need to make sure that within a certain range, the parameters that I'm setting are working, that things don't have absolute values, that they're only within an acceptable range.

Have you provided these for reference?

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