Part Number:AM4376
Hi there,
I am doing SI analysis of DDR3 Interface as a pri simulation, following the 5.13.8.2.1 DDR3 and DDR3L Routing Guidelines in the AM437x Data Sheet.
But I could not get a good SI result in the case of CK/ADDR_CNTL group signals based on "fly-by" topology recommended at the Guideline.
-> Please refer to the <A> of the figures in the attached file.
I tried the "balanced T" topology to these signals, and I got a good SI result on it.
->Please refer to the <B> of the figure in the attached file.
From these two results, I think I should adopt the "balanced T" topology to the groupe signals, not the "fly-by" topology.
Therefore, I would like to know the following conditions in this case.
1. maximum length of the CL/ADDR_CNTL signals
2. maximum skew between the CL/ADDR_CNTL signals
And if there is any concern of my decision, let me know.
Regards,
Shinji
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