Hi,
I couldn't find the difference between SPI and SCI (UART)..More or less they both are doing the same operation.
If So, then what is the need to have both in MCU?
Regards,
Varun
↧
Difference between SPI and UART(SCI)
↧
Does SN6501 have thermal shutdown ?
↧
↧
BLE stack running on CC2541 losing connectivity with client
Hi,
Design Details: We are developing an ECG device that streams multi channel ECG wave data over Bluetooth Low energy to any external android phone / tablet. We use TI's BLE chip CC2541 and TI's own BT/BLE stack for this.
Link to TI BLE Stack download : www.ti.com/.../ble-stack
The Issue Faced:
We made our ECG Front end working and we are able to input the ECG data to the BLE CC2541's 8051 core through serial communication. However, while streaming this ECG data to an android phone over BLE, we face a strange behaviour, as described below.
"The BLE connectivity with the android client is lost quite often, and almost every time."
Please note that we are able to acquire ECG data of 1.5 KBPS over the serial communication at the BLE CC2541's 8051 core through serial communication (from the front end) even when the BLE connection with the android phone is lost. We could confirm that the 8051 core is running without any resets or without any major real time issues.
Queries:
1. Has anyone tried integrating TI's BLE stack for (We use TI's BLE chip CC2541 and TI's own BT/BLE stack for this) the data rates of 9 KBPS?
2. We could get the basic heart rate transfer program working without any hassles. That make us assume that the issues are caused by high rate of data samples. Do you think this may be linked to any memory allocation/memory leaks within the BLE stack / application layer, that eats up available memory in some short period of time?
3. Are you aware of any debug handles in the stack, that can configure and debug for BLE states, heap memory information etc.? If so, how to configure and use them for code debugging?
4. Any other direction you would want to suggest for us to fix this BLE connectivity problem?
Warm Regards,
Sarang
↧
field_merging issue for pal:
hi ,
Iam using following:
hdvpss_01_00_01_44
psp: linux-2.6.37-psp04.04.00.01
width:720 && height :576 && pitch :720*2
capture_mode :8 bit && discrete sync
Iam getting output as below please suggest me changes or please kindly provide hdvpss_firmware working for pal (720*576) in field merged mode.
regards,
karthik
↧
AM3352 MLO Barebox booting problem
Hello,
we have a phycore module with AM3352 processor and NAND flash 1GB. (http://phytec.com/products/system-on-modules/phycore/am335x/)
We have own baseboard for these module. It's generally works fine but sometimes we have problem with MLO which is located on NAND memory.
The error sfrom Barebox MLO are like this:
barebox 2013.07.0-PD13.1.0 MLO PCM-051-23102F0I.A0_V1 #1 Wed Sep 18 13:48:56 CEST 2013
Board: Phytec phyCORE-AM335x
omap-hsmmc omap4-hsmmc0: registered as omap4-hsmmc0
mci0: registered disk0
m25p80 m25p800: unrecognized JEDEC id ffffff
m25p80 m25p800: probe failed: error 19
probe buswidth
nand: ONFI param page 0 valid
nand: ONFI flash detected ...
nand: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron MT29F8G08ADADAH4), page size: 2048, OOB size: 64
booting from NAND
unable to handle paging request at address 0x422ffa13
pc : [<402f9192>] lr : [<402f4b87>]
sp : 87ffff78 ip : 00000016 fp : 00029940
r10: 00029940 r9 : 402f0409 r8 : 4030cdcc
r7 : 08000000 r6 : 86ffdc88 r5 : 422ffa13 r4 : 402fd28f
r3 : 00000000 r2 : 00000000 r1 : 422ffa13 r0 : 86ffdc88
Flags: nZCv IRQs off FIQs on Mode SVC_32
no stack data available
or
barebox 2013.07.0-PD13.1.0 MLO PCM-051-23102F0I.A0_V1 #1 Wed Sep 18 13:48:56 CEST 2013
Board: Phytec phyCORE-AM335x
undefined instruction
pc : [<402fcef4>] lr : [<402fcef3>]
sp : 87ffffa8 ip : 00000800 fp : 00100000
r10: 86ffe000 r9 : 4030299c r8 : 00000c00
r7 : 00400000 r6 : 4030299c r5 : 870fdc01 r4 : 86ffa820
r3 : 0000003f r2 : 00000040 r1 : 87ffc000 r0 : 87ffc000
Flags: nZCv IRQs off FIQs on Mode SVC_32
no stack data available
I also checked the trace vectors and output is this:
CONTROL: device_id = 0x2b94402e
* AM335x family
* Silicon Revision 2.1
PRM_DEVICE: PRM_RSTST = 0x00000003
* Bit 0 : GLOBAL_COLD_RST
* Bit 1 : GLOBAL_WARM_RST
CONTROL: control_status = 0x00820333
* SYSBOOT[15:14] = 10b (25 MHz)
* SYSBOOT[11:10] = 00b No GPMC CS0 addr/data muxing
* SYSBOOT[9] = 0 GPMC CS0 Ignore WAIT input
* SYSBOOT[9] = 1 GPMC CS0 Use WAIT input
* Device Type = General Purpose (GP)
* SYSBOOT[7:6] = 00b MII (EMAC boot modes only)
* SYSBOOT[5] = 1 CLKOUT1 enabled
* Boot Sequence : NAND -> NANDI2C -> MMC0 -> UART0
ROM: Current tracing vector, word 1 = 0x0010009e
* Bit 1 : [General] Entered main function
* Bit 2 : [General] Running after the cold reset
* Bit 3 : [Boot] Main booting routine entered
* Bit 4 : [Memory Boot] Memory booting started
* Bit 7 : [Boot] GP header found
* Bit 20 : [Configuration Header] CHSETTINGS found
ROM: Current tracing vector, word 1 = 0x00018000
* Bit 15 : [Memory Boot] Memory booting trial 3
* Bit 16 : [Memory Boot] Execute GP image
ROM: Current tracing vector, word 1 = 0x00000020
* Bit 5 : [Memory Boot] Memory booting device MMCSD0
ROM: Current copy of PRM_RSTST = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000000
ROM: Cold reset tracing vector, word 1 = 0x00000003
* Bit 0 : [Memory Boot] Memory booting device NULL
* Bit 1 : [Memory Boot] Memory booting device XIP
Cortex A8 Program Counter = 0x00025568
ROM Exception Vectors
* 0x4030CE04 Undefined
* 0x4030CE08 SWI
* 0x4030CE0C Pre-fetch abort
* 0x4030CE10 Data abort
* 0x4030CE14 Unused
* 0x4030CE18 IRQ
* 0x4030CE1C FIQ
ROM Dead Loops
* 0x00020080 Undefined exception default handler
* 0x00020084 SWI exception default handler
* 0x00020088 Pre-fetch abort exception default handler
* 0x0002008C Data exception default handler
* 0x00020090 Unused exception default handler
* 0x00020094 IRQ exception default handler
* 0x00020098 FIQ exception default handler
* 0x0002009C Validation test PASS
* 0x000200A0 Validation test FAIL
* 0x000200A4 Reserved
* 0x000200A8 Image not executed or returned
* 0x000200AC Reserved
* 0x000200B0 Reserved
* 0x000200B4 Reserved
* 0x000200B8 Reserved
* 0x000200BC Reserved
Can you have any idea where is problem, is it problem with NAND ? If the MLO is reflashed then the box is running OK.
Is it there any way how to solve this problem ?
Thanks.
Tomas Krcka
↧
↧
DRV8662 first-order & Second-order filter formula
Hi,
May I know what's DRV8662 filter formula for first-order & Second-order schematic design as below?
Thanks.
↧
Trouble with network card: libphy not found
Hi Forum,
I am having problem loading on demand an Ether net driver for the Micrel chip set KSZ8081 in to the kernel.
I have following setting in kernel ".config" file
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
#CONFIG_KS8851=y
#CONFIG_KS8851_MLL=y
# CONFIG_NET_VENDOR_MICROCHIP is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_ETHOC is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
#CONFIG_NET_VENDOR_RENESAS=y
#CONFIG_NET_VENDOR_ROCKER=y
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
#CONFIG_NET_VENDOR_SMSC=y
#CONFIG_SMC91X=y
# CONFIG_SMC911X is not set
#CONFIG_SMSC911X=y
# CONFIG_SMSC911X_ARCH_HOOKS is not set
# CONFIG_NET_VENDOR_STMICRO is not set
CONFIG_NET_VENDOR_TI=y
CONFIG_TI_DAVINCI_EMAC=y
CONFIG_TI_DAVINCI_MDIO=y
CONFIG_TI_DAVINCI_CPDMA=y
CONFIG_TI_CPSW_PHY_SEL=y
CONFIG_TI_CPSW_ALE=y
CONFIG_TI_CPSW=y
# CONFIG_TI_CPTS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_PHYLIB=y
CONFIG_MICREL_KSZ8081=y # ENABLE / DISABLE of these constant in the .config give
CONFIG_MICREL_KSZ8091=y # Network driver load on demand basis. or auto load basis
CURRENTLY am335x-boneblack.dtb contents... only ether net section...as follow:
ethernet@4a100000 {
compatible = "ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <0x35 0x36>;
clock-names = "fck", "cpts";
cpdma_channels = <0x8>;
ale_entries = <0x400>;
bd_ram_size = <0x2000>;
no_bd_ram = <0x0>;
rx_descs = <0x40>;
mac_control = <0x20>;
slaves = <0x2>;
active_slave = <0x1>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <0x1d>;
reg = <0x4a100000 0x800 0x4a101200 0x100>;
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <0x1>;
interrupts = <0x28 0x29 0x2a 0x2b>;
ranges;
syscon = <0x2f>;
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x37>;
pinctrl-1 = <0x38>;
mdio@4a101000 {
compatible = "ti,davinci_mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
ti,hwmods = "davinci_mdio";
bus_freq = <0xf4240>;
reg = <0x4a101000 0x100>;
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x39>;
pinctrl-1 = <0x3a>;
linux,phandle = <0x3b>;
phandle = <0x3b>;
};
slave@4a100200 {
mac-address = [00 00 00 00 00 00];
phy_id = <0x3b 0x0>;
phy-mode = "rmii";
};
slave@4a100300 {
mac-address = [00 00 00 00 00 00];
phy_id = <0x3b 0x3>; <-----------------------------Modification implemented here.
phy-mode = "rmii";
};
cpsw-phy-sel@44e10650 {
compatible = "ti,am3352-cpsw-phy-sel";
reg = <0x44e10650 0x4>;
reg-names = "rmii-sel";
rmii-ref;
};
};
KERNEL LOG
[ 2.305710] mousedev: PS/2 mouse device common for all mice
[ 2.311656] i2c /dev entries driver
[ 2.320080] omap_hsmmc 48060000.mmc: Got CD GPIO
[ 2.405224] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.415065] oprofile: using arm/armv7
[ 2.420999] Initializing XFRM netlink socket
[ 2.426160] NET: Registered protocol family 17
[ 2.431077] NET: Registered protocol family 15
[ 2.436877] Key type dns_resolver registered
[ 2.441882] omap_voltage_late_init: Voltage driver support not added
[ 2.448763] sr_dev_init: No voltage domain specified for smartreflex0. Cannot initialize
[ 2.457374] sr_dev_init: No voltage domain specified for smartreflex1. Cannot initialize
[ 2.469023] ThumbEE CPU extension supported.
[ 2.473635] Registering SWP/SWPB emulation handler
[ 2.478916] SmartReflex Class3 initialized
[ 2.502332] mmc0: host does not support reading read-only switch, assuming write-enable
[ 2.524233] mmc0: new high speed SDHC card at address b368
[ 2.546816] mmcblk0: mmc0:b368 USD 3.71 GiB
[ 2.562923] mmcblk0: p1 p2
[ 2.574196] tps65217 0-0024: Read from reg 0x16 failed
[ 2.579655] vdds_dpr: failed to enable
[ 2.592625] tps65217 0-0024: failed to register tps65217-pmic regulator
[ 2.600007] tps65217-pmic: probe of tps65217-pmic failed with error -121
[ 2.619569] tps65217 0-0024: Failed to read revision register: -121
[ 2.628282] tps65217: probe of 0-0024 failed with error -121
[ 2.636028] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
[ 2.658698] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
[ 2.744139] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 2.750608] davinci_mdio 4a101000.mdio: detected phy mask fffffff6
[ 2.771034] libphy: 4a101000.mdio: probed
[ 2.775601] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[ 2.784144] davinci_mdio 4a101000.mdio: phy[3]: device 4a101000.mdio:03, driver unknown
[ 2.795638] cpsw-phy-sel 44e10650.cpsw-phy-sel: invalid resource
[ 2.802240] cpsw-phy-sel: probe of 44e10650.cpsw-phy-sel failed with error -22
[ 2.810875] cpsw 4a100000.ethernet: Detected MACID = 68:c9:0b:7c:e1:a1
[ 2.826378] hctosys: unable to open rtc device (rtc0)
[ 2.831761] sr_init: No PMIC hook to init smartreflex
[ 2.837949] sr_init: platform driver register failed for SR
[ 2.954203] EXT4-fs (mmcblk0p2): mounted filesystem without journal. Opts: (null)
[ 2.962613] VFS: Mounted root (ext4 filesystem) readonly on device 179:2.
[ 2.989835] devtmpfs: mounted
[ 2.995773] Freeing unused kernel memory: 432K (c0846000 - c08b2000)
[ 3.343312] EXT4-fs (mmcblk0p2): warning: mounting unchecked fs, running e2fsck is recommended
[ 3.362660] EXT4-fs (mmcblk0p2): re-mounted. Opts: (null)
Starting logging: OK
Initializing random number generator... [ 4.011504] random: dd urandom read with 11 bits of entropy available
done.
Starting network...
/etc/init.d/S93-am335x-pm-firmware-load: line 4: can't create /sys/devices/ocp.2/44d00000.wkup_m3/firmware/am335x-pm-firmware.bin/loading: nonexistent y
/etc/init.d/S93-am335x-pm-firmware-load: line 5: can't create /sys/devices/ocp.2/44d00000.wkup_m3/firmware/am335x-pm-firmware.bin/data: nonexistent diry
/etc/init.d/S93-am335x-pm-firmware-load: line 6: can't create /sys/devices/ocp.2/44d00000.wkup_m3/firmware/am335x-pm-firmware.bin/loading: nonexistent y
gwcs1x login: [ 8.432265] EXT4-fs error (device mmcblk0p2): ext4_mb_generate_buddy:758: group 16, block bitmap and bg descriptor inconsistent: 32251s
[ 8.505515] EXT4-fs error (device mmcblk0p2): ext4_mb_generate_buddy:758: group 17, block bitmap and bg descriptor inconsistent: 31328 vs 31124 frees
ETHER NET DRIVER KSZ8081 DRIVER CRASH
=====================================
gwcs1x login: root
# insmod ksz8081.ko # on demand basis
# ifconfig eth0 192.168.1.12 up
[ 54.859759] net eth0: initializing cpsw version 1.12 (0)
[ 54.944608] net eth0: phy found : id is : 0x221560
[ 54.950098] Unable to handle kernel NULL pointer dereference at virtual address 00000084
[ 54.958847] pgd = de530000
[ 54.961722] [00000084] *pgd=9e50b831, *pte=00000000, *ppte=00000000
[ 54.968509] Internal error: Oops: 17 [#1] SMP ARM
[ 54.973477] Modules linked in: ksz8081(O)
[ 54.977762] CPU: 0 PID: 79 Comm: ifconfig Tainted: G O 4.2.0-rc6-gec3fe91-dirty #2
[ 54.986924] Hardware name: Generic AM33XX (Flattened Device Tree)
[ 54.993342] task: de4e3140 ti: de490000 task.ti: de490000
[ 54.999068] PC is at cpsw_phy_sel+0x3c/0x70
[ 55.003501] LR is at bus_find_device+0x78/0x8c
[ 55.008195] pc : [<c0486380>] lr : [<c03e0828>] psr: 600d0013
[ 55.008195] sp : de491dc0 ip : de4e3160 fp : 00000000
[ 55.020264] r10: 00000000 r9 : de511740 r8 : 00000000
[ 55.025770] r7 : de425600 r6 : 00000006 r5 : 00000000 r4 : de14b410
[ 55.032646] r3 : 3f6baba8 r2 : 00000000 r1 : 00000006 r0 : 00000000
[ 55.039533] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 55.047040] Control: 10c5387d Table: 9e530019 DAC: 00000015
[ 55.053094] Process ifconfig (pid: 79, stack limit = 0xde490218)
[ 55.059419] Stack: (0xde491dc0 to 0xde492000)
[ 55.064027] 1dc0: de425000 00000002 de4772f4 c0489290 00000000 00000003 00000000 c05a55a8
[ 55.072645] 1de0: 00000000 00000000 c05a5488 c0089afc 00000000 c095ffdc c095a4ac fffffff8
[ 55.081268] 1e00: 00000000 00000000 de491e4c de511740 0000000d c005ec78 ffffffff de425000
[ 55.089882] 1e20: 00001043 c063d6e0 00001002 00000000 00000000 c005ecd4 00000000 de425000
[ 55.098502] 1e40: 00000000 c063d6e0 de425030 00000000 00000000 c04fea5c c04fe9c0 de425000
[ 55.107117] 1e60: 00001043 00000001 00001002 c04feccc de425000 00000140 00001002 00000000
[ 55.115745] 1e80: 00000000 c04fedb0 de511740 de471a0c bea71ba0 00000000 00008914 c056bb68
[ 55.124365] 1ea0: 00000020 de471a00 de471a0c de425000 30687465 00000000 00000000 00000000
[ 55.132987] 1ec0: 00001043 0c01a8c0 00000001 00000000 00000000 00008914 ddab4040 bea71ba0
[ 55.141611] 1ee0: c0959340 00008914 de490000 ddab4060 bea71ba0 c04dfb88 c04dfb18 c0175ec8
[ 55.150228] 1f00: de0322c0 00000003 bea71ba0 c017582c c0065464 de186018 de4e3140 de4e3140
[ 55.158849] 1f20: dfa1c590 00000000 de4ad800 c0967d48 dfa1c580 de184ec0 de491f8c c05e76f4
[ 55.167460] 1f40: de4d0d98 c01439fc 00100073 00000000 00000000 c05e7d88 00000000 00000000
[ 55.176072] 1f60: c5bd2670 de0322c0 de0322c0 00000000 bea71ba0 00008914 de490000 00000003
[ 55.184689] 1f80: 000be008 c0175ec8 0009e39a 0009e39a bea71ba0 bea71d8c 00000036 c000f7c4
[ 55.193311] 1fa0: 00000000 c000f5e0 0009e39a bea71ba0 00000003 00008914 bea71ba0 0009e39a
[ 55.201929] 1fc0: 0009e39a bea71ba0 bea71d8c 00000036 0008b5a8 00000003 bea71eaa 000be008
[ 55.210544] 1fe0: 000bb2d8 bea71b3c 00017c7c b6eedc26 200d0030 00000003 b7df5ffe 533f7fff
[ 55.219186] [<c0486380>] (cpsw_phy_sel) from [<c0489290>] (cpsw_ndo_open+0x9c/0x608)
[ 55.227362] [<c0489290>] (cpsw_ndo_open) from [<c04fea5c>] (__dev_open+0x9c/0x104)
[ 55.235347] [<c04fea5c>] (__dev_open) from [<c04feccc>] (__dev_change_flags+0x88/0x14c)
[ 55.243786] [<c04feccc>] (__dev_change_flags) from [<c04fedb0>] (dev_change_flags+0x18/0x48)
[ 55.252695] [<c04fedb0>] (dev_change_flags) from [<c056bb68>] (devinet_ioctl+0x67c/0x774)
[ 55.261327] [<c056bb68>] (devinet_ioctl) from [<c04dfb88>] (sock_ioctl+0x70/0x2cc)
[ 55.269319] [<c04dfb88>] (sock_ioctl) from [<c017582c>] (do_vfs_ioctl+0x78/0x6b0)
[ 55.277215] [<c017582c>] (do_vfs_ioctl) from [<c0175ec8>] (SyS_ioctl+0x64/0x74)
[ 55.284939] [<c0175ec8>] (SyS_ioctl) from [<c000f5e0>] (ret_fast_syscall+0x0/0x54)
[ 55.292926] Code: e59f0034 ebfd690d e1a01006 e1a02005 (e5903084)
[ 55.299543] ---[ end trace 172496384e6a3643 ]---
Segmentation fault
# [ 170.943936] random: nonblocking pool is initialized
[ 303.843925] EXT4-fs (mmcblk0p2): error count since last fsck: 273
[ 303.850385] EXT4-fs (mmcblk0p2): initial error at time 3: ext4_mb_generate_buddy:758
[ 303.858564] EXT4-fs (mmcblk0p2): last error at time 8: ext4_mb_generate_buddy:758
I will be grateful if you please give your valuable observation advise.
Thank you,
IK
↧
AM3352 boot ethernet and usb
Hi,
We are designing a new board based on AM3352.
Due to space constraints we have provided only Ethernet (GMII1) and USB0 (Host) interface.
initially eMMC is blank.
Our query......
During first time initial board programming / production eMMC flash programming.....
1) Is it possible to program / update flash in eMMC through Ethernet......?
2) Is it possible to program / update flash in eMMC using USB0 (Host) (binary Image in external pen drive )......?
3) Is it possible to program / update flash in eMMC using USB0 (Device), if we provide jumper to id pin......?
↧
A beginner question about GIPOLOCK and GPIOCR
There is a statement in the tm4c123gh6pm.pdf file, at page 684, under the GPIOLOCK register section:
"...A write of any other value or a write to the GPIOCR register reapplies the lock, preventing any register updates...."
Which means according to me is; after an un-lock sequence, if I change GPIOCR register, I don't need to re-lock it again by writing into GPIOLOCK. Am I right?
↧
↧
TPS40210-Q1 EMI performance
Hello,
Are there any EMI data of TPS40210-Q1?
Our cusotmer using the MAX16990 which has the Spread spectrum function.
We are promoting the TPS40210-Q1 to the customer but they can't change due to the TPS40210-Q1 doesn't have the Spread spectrum function.
If we can show the TPS40210-Q1 EMI performance which is better than MAX16990, they may consider to use our device.
Best Regards,
Ryuji Asaka
↧
UDP connection using LWIP
hello,
i use udp connection between AM437x IDK "using sdk " and AM437x EVM "using QT app " and it's connected successfully but when sent alot of data packets like 270 packets and call udp_sentto() function again get some error and goes to infinite loop " i think ".
anyone have solution to solve this issue ??
↧
Execution time issue SARAM/XINTF
Hi,
on F28335 I have observed that when I mix access to internal SARAM (L7) and SRAM on XINTF, the code executes substantially slower than when all accesses are on internal memory. This is also valid for part of code that exclusively manipulates SARAM data if it is preceded and followed by accesses to external memory. I'm guessing this has something to do with emptying the pipeline before switching memory but I would like to get a confirmation for my theory. Tried looking for an explanation in the documentation, but with no success.
Am I right in my guesses or something else is going on?
Regards,
Josip
↧
Archive symbol directory is missing from archive (Macro archive)
Hello,
I am trying to create a macro library for the first time.
I follow step by step the indications written in ARM Assembly Language Tools v5.1 User's Guide.
I got an assR18.lib file after the command:
c:\ti\ccsv6\tools\compiler\ti-cgt-arm_5.2.2\bin\armar.exe -@assRlibCommands.cmd
Then I placed the assR18.lib file in the Include directory and I cleaned the project.
I got the following warning:
#10189-D archive symbol directory is missing from archive "../include_appli/assR18.lib"
If I replace in source file “.Include assR18.asm” by “.Include assR18.lib” There is no illegal mnemonic error and the compilation seems to be good except that the project is not remade because of error:
gmake: Target `all' not remade because of errors.
**** Build Finished ****
The compiler does not tell us anything about the error.
I tried to build an archive with the following command:
c:\ti\ccsv6\tools\compiler\arm_5.1.5\bin\armlibinfo.exe -o=assR18_Arch.lib assR18.lib
I got a file with only one line inside:
!<arch>__TI_$$LIBINFO/ 1441178127 0 0 0 0
What can I do?
Thanks a lot for your help
Jerome
↧
↧
How to read ADS1298 ID register, write other registers
Hi,
I have a SR open(SR#: 1-1893850773) in ti-china@ti.com, they recommend me to this forum.
I'm operating ADS1298 with STM32F4xx, but I always fail to run command RREG and WREG.
so that I always get DRDY signal with rate of SPS 250, which is the default value after reset.
Following is my code, which I wrote according to the user manual with the reference of a lot of web pages.
I hope I can get some help from you, pointing where I'm wrong,
or you can give a copy of sample code that I can successfully read out the ID register or write into other configuration registers(because they said e2e forum has source code).
My dev environment is: ADS1298,STM32F407VGTx,Keil uVision5,STM32Cube_FW_F4_V1.7.0
Also, I attached one snapshot of timming diagram I got out.
Thanks
Marcus
uint8_t datarx[26];
SetCSValue(0); //Set CS PIN LOW
SetPWDNValue(1); //Set PWDN PIN HIGH
SetRESETValue(1); //Set RESET PIN HIGH
HAL_Delay(1000); //Sleep 1 Second
SetRESETValue(0); //Set RESET PIN LOW
HAL_Delay(100); //Sleep 100 mini second
SetRESETValue(1); //Set RESET PIN HIGH
HAL_Delay(100); //Sleep 100 mini second
//SDATAC
SDATAC_Command(); //Send SDATAC Command
//RREG
memset(datarx,0,sizeof(datarx));
RREG_Command(0x20,0,datarx,1); //RREG Command, read only ID register, aways return 0x00,check the diagram for command sequence
void SDATAC_Command()
{
uint8_t data = 0x11;
SetCSValue(0);
HAL_SPI_Transmit(&hspi2,&data,1,1);
HAL_Delay(1); //Sleep 1 mini second then set CS HIGH
SetCSValue(1);
}
void RREG_Command(uint8_t opcode1, uint8_t opcode2, uint8_t* datarx, uint8_t len)
{
uint8_t datatx[26];
memset(datatx,0,sizeof(datatx));
SetCSValue(0);
HAL_SPI_Transmit(&hspi2,&opcode1,1,1);
HAL_Delay(1);
HAL_SPI_Transmit(&hspi2,&opcode2,1,1);
HAL_Delay(1);
for(int i=0;i<len;i++)
{
HAL_SPI_TransmitReceive(&hspi2,&datatx[i],&datarx[i],1,1);
}
HAL_Delay(1);
SetCSValue(1);
}
With the following SPI configuration:
hspi2.Instance = SPI2;
hspi2.Init.Mode = SPI_MODE_MASTER;
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_SOFT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLED;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
hspi2.Init.CRCPolynomial = 10;
HAL_SPI_Init(&hspi2);
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BQ24295 PMID and SYS pins
Hi
I see that charger chips like the BQ24272 have the PMID pin but it's not recommended to be connected to an external load.
However, BQ24295 has a PMID pin as well but it's designed to boost the voltage for an external load. That said, it seems that it's active only when VBUS is inactive (8.3.1.3) - or is it? Does that mean PMID is inactive during charge mode?
But looking at the block diagram, it looks like VBUS passes current to PMID.
If the device is to pull current regardless of the state of VBUS, how should it be hooked up? It'd be in vain if it's connected to PMID alone (similar to the example circuit) as there'd be no power when the input source is present. Isn't the load usually connected to SYS? They call SYS the 'system connection point' whilst PMID the 'battery boost mode output voltage'.
In fact, what does PMID actually stand for?
Thanks
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My MSP432 is drawing 170 mA. Why?
Hi.
I got MSP432 launchpad a week ago.
Studying MSP430 LaunchPad Workshop Course Workbook as my textbook. There was no problem whatsoever. But in lab 7(Energy trace) I've encountered a problem.
After flashing solution of lab_07b_lpm_timer project. I ran EnergyTrace. But EnergyTrace immediately stops and it saids "Target current exceeded with the maximum current (75mA) supported by EnergyTrace."
Huh?
So I actually measured current and voltage with my multimeters and the uc was drawing 170 mA. Even in reset state.
No external circuitry has ever connected to my launchpad. Even no single jumper wire.
What could be a cause of this problem? ESD?
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No option for rehost my float licence.
No option for rehost my float licence.
also another question , Can I install the license in my virtualbox win7 ?
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RAM allocation on Keystone2
Hi,
I use men_reserve to allocate memory for ARM and DSP cores,
Is there a way to make sure that theses cores won't cross the border during writing/reading?
Any help in this regard is appreciated.
Regards
Kevin.
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Negative temperature with LM35DZ/NOPB
Hi!
I am planning to use the LM35DZ sensor for overheat-protection (temperature range 50 to 90°C). I would like to use the simplest circuit with single supply and without offset (Diode, etc.). The problem is that at start up the temperature can be negative, later self-heating will ensure a positive temperature. I don’t want to measure the negative temperature, but I expect to read a low temperature, if the temperature is negative.
Is the Vout nearly 0V, if the temperate is below zero degrees?
-Thomas
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TM4C1294 production programmer
Hello!
Suggest me please a production programmer for TM4C1294, which can work with LMFlash Programmer tool or can programm the User Register of this micro.
We used for this purpose a part of development boards before (EK-TM4C1294XL and EK-TM4C123GXL) but something was wrong, and both of these programmers was broken.
Thanks in advance for any recommendations!
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