Part Number:TMS320F28379D

Hi, 

I'm using one CLA of the TMS320F28379D to do some SPI transfer management (filling TX and emptying RX buffers).

(NB: I cannot use the DMA, due to the fact that I use the CLA for some regulation loops that access one peripheral on the same peripheral frame).

I need to reconfigure the task trigger depending on the progress of the SPI transfer (first time the task is triggered by PWM module than following transfers are triggered by an SPI transfer interrupt).

Is the CLA capable of accessing its own configuration registers?

Thank you in advance ;)

Part Number:BQ27441-G1

Hello I'm able to write on any other data memory locations, however I can't do so for security codes subclass. I have tried to write two equal 16-bits operations  and as a single 32-bit operation. but nothing is done in both scenarios, reading it again it always returns the default value. The device is unsealed and CFGUPMODE is set.

Is there anything else I have to do to write on that memory location?

Thanks in advance

Part Number:TPS6735

Hello, 

What is the input current limit on the EN pin? I want the EN pin to always be enabled. 

Can I just tie it to the VDD or will the EN pin get fried?

Regards, 

Juliana

Part Number:MSP430G2553

Tool/software: Code Composer Studio

Hi there,

as part of a own project i want to interprete the DCF77 signal, which is a radiosignal in germany containing the current time and alot more informations. As a start I want to detect a change of the voltage level in the signal.

About the DCF77 signal: It remains in digital high state and drops to digital low for a short part of a second. If the duration takes 100 ms it is adequate to a "0", if it takes 200 ms it is a "1". That way there is one bit in every second of the signal.

Setup: I use a DCF77 module from Conrad. The picture below shows the setup with the MSP430 Launchboard.

The signal output signal (I marked it with the letter "d" and the inverted with a d with a bar over it) comes from an open npn transistor. With my osci I am able to detect the signal:

As the voltage is pretty low i am using an internal pullup restitor of the msp. My code is the following one:

#include <msp430.h>
#define Sensor BIT7
#define LED BIT0

int main(void)
{
    WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
 
    P1DIR = 0xFF;                            // all Ports to Output
    P1DIR &= ~Sensor;                        // Sensor port to Input
 
    P1REN = Sensor;                 // Enable internal pull-up/down resistor
    P1OUT = 0;                        // All Outputs to digital low
    P1OUT = Sensor;                 // Select pull-up mode for Sensor port
 
    P1IE = Sensor;                       // interrupt enabled
    P1IES = Sensor;                     // Hi/lo edge
    P1IFG &= ~Sensor;                  // IFG cleared
}

#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
    P1IFG &= ~Sensor;                  // IFG cleared
    P1OUT ^= LED;
}

My problem is that the interrupt doesn't occur. Could it be that the internal pullup isn't enough or did I missunderstand the usage of it? Or does someone see a mistake in  my code?

I am thankfull for every hint, this problem bothers me since a while.

Part Number:BQ24650

I am looking at the BQ24650 particularly at "converter operation" in the datasheet. I notice that it is mentioned twice in the both "Device Functional Modes," and "Feature Description." These descriptions are on page 13 and page 20 of the datasheet. When describing the converter operation, the description is the exact same for these two sections but in "Feature Description" is mentions an optimal range of 12-17kHz while in "Device Functional Modes" it mentions an optimal range of 17-25kHz. In Feature description, it carries this range forward to give inductor, capacitor and sense resistor recommendations but is this 17-25kHz range something else? 

Thanks,

Beau

Part Number:BOOSTXL-TLV8544PIR

I have a CC2650 Launchpad + BOOSTXL-TLV8544PIR and I am trying to get the two boards to transmit the PIR sensor data wirelessly. In the BOOSTXL-TLV8544PIR User's Guide it states: "this board design could easily be used as the basis for an ultra-low power, battery-operated, wireless PIR or microwave motion sensing system, further simplifying design and speeding time to market." Is there a document that explains how this is done? I found a few TI Designs that seem to use similar hardware and already have firmware (TIDA00759 and TIDA01398). Is there a simple way to flash this firmware to the CC2650 Launchpad and use it with the BOOSTXL-TLV8544PIR?

Thanks,

Matt

Part Number:TMS320F28377S

Hello there,

We've developed a custom bootloader application that is used to update the main application. The firmware update process worked without problems before enabling the code security module. Our custom bootloader was able to erase the flash used by the application, download and write to flash the new application, then validate the new application code using a CRC and at last start the new application.

In order to make things easier we use only Zone 1 and allocated all flash and secure RAM to Zone 1 as shown below:

      .sect "dcsm_otp_z1_linkpointer"
;;    .long 0x1FFFFFFF     ;Z1-LINKPOINTER1
;;    .long 0xFFFFFFFF     ;Reserved
;;    .long 0x1FFFFFFF     ;Z1-LINKPOINTER2
;;    .long 0xFFFFFFFF     ;Reserved
;;    .long 0x1FFFFFFF     ;Z1-LINKPOINTER3
;;    .long 0xFFFFFFFF     ;Reserved

      .sect "dcsm_otp_z1_pswdlock"
    .long 0xFFFFFF0F     ;Z1-PSWDLOCK   - protect the password
    .long 0xFFFFFFFF     ;Reserved

      .sect "dcsm_otp_z1_crclock"
;;    .long 0xFFFFFFFF     ;Z1-CRCLOCK
;;    .long 0xFFFFFFFF     ;Reserved

      .sect "dcsm_otp_z1_bootctrl"
;;    .long 0xFFFFFFFF     ;Reserved
;;    .long 0xFFFFFFFF     ;Z1-BOOTCTRL

      .sect "dcsm_zsel_z1"

    .long    0xFFFFFFFF      ;Z1-EXEONLYRAM
    .long    0xFFFFFFFF      ;Z1-EXEONLYSECT
    .long    0x10005555      ;Z1-GRABRAM    - CLA, all RAM blocks for Zone 1
    .long    0x15555555      ;Z1-GRABSECT   - Bank 1 and all flash sectors for Zone 1

    .long    0x11111111      ;Z1-CSMPSWD0 (LSW of 128-bit password)
    .long    0x22222222      ;Z1-CSMPSWD1
    .long    0x33333333      ;Z1-CSMPSWD2
    .long    0x44444444      ;Z1-CSMPSWD3 (MSW of 128-bit password)

As all flash is allocated to Zone 1 the application runs from secure memory. The "ramfunc" is also placed in secure RAM (RAMD0 & RAMD1), tasks' stack is located also in secure memory RAMLS0-5. We use the non-secure RAMGS4-11 blocks for the ".cio", ".esysmem", ".ebs", DMA buffers, and an external SRAM for heap.

After enabling the code security module our custom bootloader is still able to erase the flash used by the application, download and write to flash the new application, validate the new application code but when the new application is started the processor hangs and I do not know where.
If I use the "Wait Boot Mode boot option" to unlock the processor and then set the PC to the application entry point (after the application was updated using our custom bootloader) the application runs fine.

How can I debug this situation to find out what is causes the CPU to hang? What else should I check?

Thanks a lot,

Doru

Part Number:TPS62080

Hello team,

Lately we have encountered some problems with the TPS62080 device that seem to be pattern dependent as it is used to generate 0.6V for VTT. Specifically it is my suspicion the device was going into low power state when the pattern is mostly or all "1's". We have a minor reowork to the board that adds a load on the output (~1.65ohm) to keep the device from going into low power state. We have been working the device very hard with this rework to see if it fails but it has been solid.

We are looking to TI to confirm our simulation in TINA is correct as well advise if adding this load resistance is a problem.

Certainly if we were creating a new design we would take the advised parts into consideration but at this time we are focused on making what we have work, reliably.(Please visit the site to view this file)

Part Number:CC3220

Hi Team SimpleLink,

My customer plans to set the Region code (in the CC3220SF) in the factory via WiFi.  Based on the applicable country of interest, the applicable region will be set (as US, EU, JP).

Many countries have been boiled down to 3 region codes by TI.. Is there any documentation to explain which of the three possible settings would be used for each possibility (for all countries in the world)?

 WRT ( http://processors.wiki.ti.com/index.php/WL18xxMOD_Regulatory_Product_Certification#Countries_Accepting_FCC.2FIC.2FCE.2FMIC_Reports )

This chart lists several countries that allow FCC or ETSI (even though FCC and ETSI have very different guidelines, both in terms of allowable power and acceptable channels). Any explanation for this?

We also have the following additional questions..

1)      Would “US” settings cover North America?  Both North and South America?

2)      It appears that only Japan uses Channel 14.  We assume that this means that the “JP” setting would be used only for Japan then; is that correct?

3)      Would “EU” cover all of Europe? 

4)      Based on 1) and 2) above, would “EU” work for everywhere in the world except for US (or North/South America) and Japan?

Thanks, Merril

Part Number:TMS570LC4357

We are using the EMIF on the TMS570LC4357 (with ARM® Cortex® - R5F). According to the Datasheet (below), the EMIF is BE8 and the device is BE32. A description is provided in the Datasheet to wire the bus to perform the format conversion.

We have a device containing a 32-bit read-only register at 0x60000024 set to 0x18101207 connected to the EMIF using the BE8/BE32 wiring given in the datasheet. We have observed that reading address offset 0x4 and 0x6 as 16-bit (Half-Word) reads the data appears correct however, when read as a 32-bit word at offset 0x4, the Half-Words are swapped. Here are the results:

Read ADDR=0x60000024, SIZE=16; return value = 0x1207 <-- expected value

Read ADDR=0x60000026, SIZE=16; return value = 0x1810 <-- expected value

Read ADDR=0x60000024, SIZE=32; return value = 0x12071810 <-- unexpected value (expected 0x18101207)

Can you explain this Half-Word swap behavior?

The Coretex-R5 manual indicates it does not support BE32 but the TMS570 Datasheet indicates this device is BE32. Can you explain this disagreement?

TMS570LC4357 datasheet (SPNS195C –FEBRUARY 2014–REVISED JUNE 2016):

The EMIF is inherently BE8, or byte invariant big endian. This device is BE32, or word invariant big endian. There is no difference when interfacing to RAM or using an 8-bit wide data bus. However, there is an impact when reading from external ROMs or interfacing to hardware registers with a 16-bit wide data bus. The EMIF can be made BE32 by connecting EMIF_DATA[7:0] to the ROM or ASIC DATA[15:8] and EMIF_DATA[15:8] to the ROM or ASIC DATA[7:0].

Alternatively, the code stored in the ROM can be linked as -be8 instead of -be32.

For a 32-bit access on the 16-bit EMIF interface, the lower 16-bits (the EMIF_BA[1] will be low) will be put out first followed by the upper 16-bits (EMIF_BA[1] will be high).

Coretex-R5 Technical Reference Manual (ARM DDI 0460D ID092411):

The processor supports byte-invariant big-endianness BE-8 and little-endianness LE. The processor does not support word-invariant big-endianness BE-32. Bit [7] of c1, Control Register is always 0.

Part Number:ADS5474-SP

Hello,

Can you check the characterization data for the ADS5474-SP?

One of our customers plans to running this converter at 200MSPS. However, all the current consumption specifications in the datasheet are measured at 400MSPS.

We would like to fill in this table:

Regards,
Ryan B.

Part Number:BEAGLEBK

Tool/software: Linux

Hi, I am having an issue with the WS and BCLK rate being produced by my system as running the McASP in I2S master mode.  I am interfacing the Beaglebone Black over I2S with a BT radio. 

When I play the 44.1kHz audio my printk() statements produce the following parameters with good audio and a scoped output to match.

[ 1022.052468] sample_size=16
[ 1022.052482] rate=44100
[ 1022.052493] sysclk=24000000
[ 1022.052496] bclk_freq=1411200

When I play the 8kHz audio my printk() statements produce the following parameters but the audio us speed up and the scoped output does not match the parameters.

[ 1081.128650] sample_size=16
[ 1081.128664] rate=8000
[ 1081.128673] sysclk=24000000
[ 1081.128677] bclk_freq=256000

My scope output produces a BCLK at 827.8kHz (rather then 256kHz) and a WS signal at 25.86kHz (rather then 8kHz).  My guess would be this has to-do with a mis-match in mapping the rates to the clock divider circuitry described in section 22.3.5.1 of spruh73p.pdf.  I am just not sure where to find this mapping inside the linux kernel drivers.  I am using 4.14.40 from the TI sdk and my drivers have been largely taken from the steps in: http://processors.wiki.ti.com/index.php/Sitara_Linux_Audio_DAC_Example.

Flip-flops, latches, and registers do not have a default state on power up.  The output is in an 'unknown' state until data is clocked through.

This is because the underlying latch circuit used to store the output value is inherently unstable at startup.  It could become a HIGH or a LOW at the output, and the value is impossible to determine before it is measured.

Part Number:LAUNCHXL-TMS57004

Hello There,

I hope you can help me here.

I'm trying to use HALCoGen for generating the headers and source files for doing the same as the example provided in TI web page to comunicate with the bq76pl455a. Unfortunately no Halcogen file is provided in that example!, please provide if available.

I believe I have configured everything correctly in Halcogen, SCI, GIO, RTI but the code stays waiting for a response from the bq76pl455a-q1.

The code is attached, if that helps.

Resistors R8 and R9 have been already removed from the launchpad.

Could you please tell me what is wrong in this code?

Kind regards,

Pere

(Please visit the site to view this file)

Part Number:FDC1004

I'm trying to set-up a liquid level sensor as per TIDU736A.

I want to test the conventional sensing first.

Can you provide information on the GUI setup for ratiometric conventional sensing (as opposed to out-of-phase sensing)? 

Part Number:TMS320C6655

Hi,

My customer is struggling with difficulties to get stable performance on their design, which seems to be related to the DDR configuration. Can someone please help us to verify the configuration below:

Settings of DDR3 SDRAM CK=666.67MHz; tCK=1/CK=1.500ns; tRCD=tRP=CL=13.75ns; Speed -125 (1.25ns or 800MHz)

DDR memory is: TN-47-02 DDR2 from Micron (www.micron.com/.../tn4702.pdf)

1. OLD SETTINGS:  Two Versions in step (iv).

(i)      CL=floor(13.75n/(1/666.67M))=9=0x9

(ii)    CWL=7 (0x7) since 1.875ns>^tCK>1.500ns

(iii)   AL arbitrarily set via step (iv) and not equal to 0, CL-1 or CL-2.

(iv)   DDR_PHY_CTRL_1[4:0]=[10=0x0A|14=0x0E] with 0x0A older and 0x0E being newer settings thus RL=CL+AL=[10+1=11=0xC|14+1=15=0xF]

1. Latest NEW SETTINGS

(i)      CL=ceiling(13.75n/(1/666.67M))=10=0xA

(ii)    CWL=7 (0x7) since 1.875ns>^tCK>1.500ns

(iii)   Selected AL=CL-2=10-2=8=0x8 to meet DDR_PHY_CTRL_1[4:0] value constraint.

(iv)   DDR_PHY_CTRL_1[4:0]=17=0x11 (Register value required is 18-1=17=0x11).This meets CL+1=10+1=11<=Register Value<=CL+7=10+7=17

We would like you to review the latest settings in (2) and also possibly comment on the settings in older versions in (1).  We are experiencing AC power drops from large fixed FFT size computation from captured samples with instability of >=0.3/0.5dB, over multiple sample intervals in time (few hours to a couple of days), and moving from older settings to new settings we have improved the instability – but still needs further improvement.  What is the implication of improper setting of CL and specifically AL (Posted CAS Additive Latency) with respect to data gap (excerpt from pp15-16 TN4702.pdf from Micron Tech. Inc.), and its impact on data read out from DDR3.

Best regards,

Joakim

Part Number:LMZ14201

A few questions on this part:

- Is the part CMOS or bipolar

- Did the part pass electrical latchup?

munir

Part Number:ADS7883

SPI signals which I sampled from ADS7883 component in my board, are attached above.

Above the signals there is a ruler with numerated ticks.

The time between each two adjacent ticks is 1/75Mhz. The SCLK is spread over 5 ticks. So it means that SCLK frequency that I use is 15Mhz.

I don't understand 3 things:

1. According to the datasheet ADS7883 is supposed to output on its SDA output 16 bits on each reading cycle.

    According to the datasheet the first 2 bits (of the 16 bits) are always zero

    So why is the first bit = ‘1’ on each reading cycle (as seen in the sampled signals above)?

2. According to the datasheet the last 2 bits (of the 16 bits) are always zero.

    So why is one of the 2 last bits on each reading cycle (as seen in the sampled signals above) different from ‘0’?

3. Why do I get the short zero on SDA signal on tick number 1722?

    I don’t understand how the data (of SDA) can be shorter than the SCLK.

Waiting for answers

Regards

Zvi

Part Number:AM3352

Using a raw nand chip for storage within a non-Linux, bare metal system that has an old RTXC rtos.

When the stored and calculated eccs differ, the ELM is then brought into play to locate the bad bit.

What is not stated anywhere other than the reference manual section under Hamming code (7.1.2.3.12.3.1.4 ) is that the two values must be XORed before loading into the ELM.

The resultant bit location from the ELM is the bit address from the end of the data stream, i.e. bit address 0 is in the last byte read.

Again, not well documented for 8 bit nand.

One other undocumented aspect of the ELM result, when the error bit is bit 0, the calculated index is one byte off.

Here is my code to correct an error :

               nBitAddr = *pu32Syndrome++;      // read from the elm result reg

               nByteAddr = 4096 - nBitAddr;     // 512 bytes * bits/byte

               nByteAddr /= 8;

               nBitAddr %= 8;

               if ( nBitAddr == 0 )

               {

                  nByteAddr--;

                  u8BitMask = 0x01;

               }

               else

               {

                  u8BitMask = 1 << nBitAddr;

               }

               pu8Data [ nByteAddr ] ^= u8BitMask;

I am using the bin2nand utility to generate loads with correctable errors and I have verified this code works to correct all the errors.

Would like confirmation that my findings are correct and am more than curious why this is.

Thank you.

Part Number:TDC1000

Hi,

My customer would like to know how the viscosity of a liquid would affect the measurements/accuracy in level sensing using TDC1000?

Thanks,

Chuchen