Part Number:TMS320F28027
Hi,
I am trying to see in debugger why I cannot rely on the RXRDY as an indicator that something has been received in SCI Rx buffer.
So far, my conclusion is that RXRDY is never set. I am using this without Rx interrupts disabled.
Please, let me know how it the SCI receiver supposed to be initialized in order to reliably receive asynchronous byte by byte ingress 8-bit data.
When is the RXRDY set, and how to condition SCIA Rx side to allow for reliable RXRDY usage?
Previously, when waiting on SCI to raise RXRDY flag, I ended up in eternal wait loop.
My workaround was to check if the FIFO is not empty, so I can read the buffer, but that is not recommended usage of Rx SCI.
Here are the details form SPRUGH1C-Revised October 2009, document by TI the following should be true:
"2.7.2 Receiver Data Buffer (SCIRXBUF)
When the current data received is shifted from RXSHF to the receiver buffer, flag bit RXRDY is set and
the data is ready to be read. If the RX/BK INT ENA bit (SCICTL2.1) is set, this shift also causes an
interrupt. When SCIRXBUF is read, the RXRDY flag is reset. SCIRXBUF is cleared by a system reset."
What am I missing here?