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Linux/DLPDLCR2000EVM: Temperature data and setting LED current

April 12, 2018, 12:03 pm
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Part Number:DLPDLCR2000EVM

Tool/software: Linux

Hi

trying to set get the temperature and LED current on the EVM connected to a raspberry pi following the thread https://e2e.ti.com/support/dlp__mems_micro-electro-mechanical_systems/video_and_data_display/f/947/p/635358/2344174?tisearch=e2e-sitesearch&keymatch=dlpc2607%20lumens#2344174 

However, unable to change the LED current to 100% duty cycle when i tried the below. 

i think i'm using the correct address and function, so help please? the raspberry pi doesn't allow the use of 0x400

also, how would I set the LED current to 25% or 50% duty cycle? would it be 0x10 and 0x20? 

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DRV8301-69M-KIT: Shorted pins due to solder

April 12, 2018, 12:03 pm
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Part Number:DRV8301-69M-KIT

I'm having issues with my board due to what looks like a drop of solder between GL_B and SL_B (pins 39 and 40) on the DRV8301. I have confirmed the short by observing the gate voltage of the low side phase B FET to be stuck at ground while running the motor identification routine in the InstaSPIN_MOTION GUI. The board instantly faults when I run this.

I received the board a week ago. What should I do?

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AWR1642: The radar detection range depth and width max at 11.16 and 5.58 meters and can not increase for my demo board?

April 12, 2018, 12:22 pm
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Part Number:AWR1642

Dear Sir/Ms:

Regarding to my demo board, I have range depth and width width max at 11.16 and 5.58 meters, if I input bigger than these ,it will con=me back automatically, does this make sense?

Thank you !

steven.

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AM5718: implementing a circular buffer FIR filter in the C6xxx DSP

April 12, 2018, 12:29 pm
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Part Number:AM5718

Hi,

We are using the C6xxx in the AM5718.

I am trying to implement a Circular buffer FIR filter preferably with 16 bit real data against a complex Kernel. 

In the DSPLIB_API reference, we saw the DSPF_sp_fircirc function, but it appears to be floating point.  Also, it is the only one of the 30 odd FIR / IIR examples to be circular.

If you can just point us in the right direction.

Thanks for the help!

Blake

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Synchronizing DLP projector (CEL5500 light engine) with a camera and controlling them via a LabView based Platform

April 12, 2018, 12:31 pm
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Hello:

We have an imaging system that consists of a digital light projector [CEL5500 light engine (with DLPC200) ] and a camera (PhotonMax:1024B). Currently, a custom-developed LabView-based GUI is used to control image acquisition and the projector is controlled using the bundled software (DLP® CELconductor Control Software), and the two components work independently from each other.

What we are going to next to integrate the two components in to the LabView platform, and automatically captures each of projected light pattern (let projector trigger camera or vice versus). My first question is to how to interface the projector with LabView. I searched some posts on the topic (https://e2e.ti.com/support/dlp__mems_micro-electro-mechanical_systems/advanced_light_control/f/387/t/468024; https://e2e.ti.com/support/dlp__mems_micro-electro-mechanical_systems/advanced_light_control/f/94/p/292004/1022485#1022485) but had no good luck.

If the projector is not controlled by LabView, is there other way to synchronize the light projection with image acquisition when the latter is done in LabView? Does an external trigger cable lining the projector and camera suffice? We want to doe some high-speed imaging experiments to take the full advantage of the projector and the camera.

Thanks

Yuzhen

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RTOS/CC2650: Low Power State on CC2650

April 12, 2018, 12:35 pm
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Part Number:CC2650

Tool/software:TI-RTOS

We recently ported our current application from Ble Stack 2_01_00_44423 to Ble Stack 2_2_1 . In the process we had to update the TI RTOS from 2_13_00_06 to 2_20_01_08.  The Port was successful and everything work perfect expect the Power . It just seems that after the port the device doesn't seems to enter lower power state and remains at 5mA  whilst our older application we were consuming ~500uA . We do have the POWER_SAVING preprocessor defined and are using NPI UART (MRDY/SRDY) as we did previously as well. Is there any further depency thats needs to be addressed in terms of power in either the ble stack 2_2_1 or TI RTOS 2_20_01_08 ? 

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TMS320F28379D: serial flash programming

April 12, 2018, 12:39 pm
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Part Number:TMS320F28379D

Hello team,

I would like to ask again the question, regarding to SCI-Boot and Boot from Flash.

As you may remember, my customer need to change the BOOT PIN to some others in order to interconnect to the SDRAM.

It is done in Z1_BOOTCTRL register in OTP of the MCU.  Till now it is OK .But this register is responsible for BMODE value.

My question is : If the customer want every time to make Boot from Flash, but sometimes SCI boot (for external program loading, not via JTAG) that value I shall enter to this field? By default, this register is  0Xffffffff . Or he shall leave those sector FF.

Another questions is : Does after new boot pin assignment they are override the BMODE value?

Thank you very much and regards,

Shai

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BQ25606: Can it differentiate between USB and power supply

April 12, 2018, 12:42 pm
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Part Number:BQ25606

Hello team,

lease see below customer question:

We are using this in an application where we will power from either USB or another discrete power supply.  While powered by the discrete power supply, we may be connected to a USB host port.  I am concerned that the charger will not know what the source of the voltage is and will negotiate the current with the USB even though it is not the source providing power (I am using your OR-ing FET controllers to supply the power to the charger).  Does the charger look at the voltage input to know if it is on a USB port?

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TPS65983B: Thunderbolt Questions

April 12, 2018, 12:45 pm
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Part Number:TPS65983B

I have a customer who is developing a Thunderbolt 3 design with the TPS65983B. He has questions regarding the SPI interface and a bin file that he generated below:

1.  I'm working this with another engineer and he had a question too.  He put an Aardvark I2C from Totalphase on the line and he saw the I2C lines polling address 0x3F.  When he acknowledged that it quit.  Is that expected behavior?

2.  I was looking at the bin file generated by Intel when I add the TPS65983B code in.  It has pointers at 0x0 and 0xFFC like I would expect.  However there are none at 0x1000 or 0x1FFC.  Also the first set is pointing to the Region Pointer in the low header.  Is this okay or do the pointers need to be adjusted per the TPS65983 Firmware User's Guide?

Please let me know if you have any further questions for the customer.

Thanks for your help with this!

Richard Elmquist

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UCC27714: HO drive stay high during LO side Cboot shoot through

April 12, 2018, 12:58 pm
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Part Number:UCC27714

Very strange issue proven software other vendors gate drivers does not cause large voltage surge during Cboot charge cycles. This issue refers to 3 phase commutation and 24VDC bus supply rising to over 90vdc with inverter loaded or not. A custom PFC was resolving 80v-90v PWM surges controlling DC bus voltage. That was the only way Cboot cycles could ever succeed let alone FOC commutation drive a connected motor to 7600RPM.

The PWM frequency 20Khz driving 500ns Cboot duty cycle (1%), user settable charge time 1-255ms. Capture below taken single phase (1/2 bridge), all phases resemble similar pattern though signals cut off in 2ms when PWM fault handling has been enabled. Otherwise the 500ns Cboot pulses POR the MCU very abruptly.  UCC pin 4 (EN) was kept high 3v2 (enabled) at all times of this testing.

How could HO drives stay on during Cboot cycles when the MCU PWM control block keeps all 3 HI (low) during Cboot cycles? Do we not expect H0 side should always be low during Cboot cycles or have I missed something in how 1/2 bridge shoot through occurs? Perhaps these 3 gate drivers are messed up in some way and do not follow proper 1/2 bridge switching conventions. The LO side gate drives pulse rising edge from ground producing the odd wave form below. The LO side seems correct in my opinion but not HO staying active during Cboot cycles so the HO single is some how being inverted.

CH2: ADC0 channel input reporting DC voltage. Signal represents 70-80V peaks from 24VDC supply low/left side of signal prior to undesired POR of MCU, far right.

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ISOW7841: Large Ripple and Sagging Voltage

April 12, 2018, 1:00 pm
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Part Number:ISOW7841

Hello,

I am working with a customer on their ISOW7841 design and we are seeing extremely large voltage ripple on the Viso output rail.

Figure 30 of the datasheet shows that Vpp should be less than 100mV at 5V full load.

In testing, the customer has 10uF on Viso and using a dummy load of 4.7kOhm or 120Ohm. See scope-shots below for the ripple they are seeing under both conditions. Note that both waveforms are averaging under 5V.

4.7kOhm:

 

120Ohm:

Let me know what steps we can take to narrow in on the issue here.

Thank you!
Ryan B.

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BQ27GDK000EVM: SW needed for EVM

April 12, 2018, 1:10 pm
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Part Number:BQ27GDK000EVM

Hello team,

Please see below customer question:

The documentation on the fuel gauge mentions some software we can run but says an EVM  BQ27GDK000EVM is needed.

Is this board needed for this and the battery charger EVM’s I have now?

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CC2640R2F: GAPCentralRole_EstablishLink detailed event generation

April 12, 2018, 1:31 pm
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Part Number:CC2640R2F

Hi, I am using the GAPCentralRole_EstablishLink call to re-link to an existing known device and that works just fine.   We have a scenario where it would be helpful to know the advertising type of the device we are connecting to. I would like to know when we are trying to re-connect if the device is advertising as GAP_ADRPT_ADV_IND or GAP_ADRPT_ADV_DIRECT_IND.  I haven't found any way to obtain that level of information while the call is processing.  Is there any way to extract this level of detail during or even after the GAP_LINK_ESTABLISHED_EVENT is sent?

Thanks,

Tim

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CCS/MSP430FR5989: Debugger stepping through code but no GPIO toggling. Tri-stated?

April 12, 2018, 1:32 pm
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Part Number:MSP430FR5989

Tool/software: Code Composer Studio

I'm running a super simple program:

int main(void)
{
    WDT_A_hold(WDT_A_BASE);
    GPIO_setAsOutputPin(GPIO_PORT_PJ, GPIO_PIN4);

    while (1)
    {
        GPIO_setOutputHighOnPin(GPIO_PORT_PJ, GPIO_PIN4);
        GPIO_setOutputLowOnPin(GPIO_PORT_PJ, GPIO_PIN4);
    }
}

I'm able to program the board via the Debugger and step line-by-line through the code.  I can see the correct Pin and Port changing when I step through the code in the Register Map.  However I'm not seeing the voltage on the physical pin changing when I probe it with a scope, it's just at 0V.  

Is there a way in which the micro could be held in some sort of reset state but the debugger still works?  Or is there a voltage that might not be connected properly that wires up the I/O Buffers?  

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TPS62821: Package Mechanical Data

April 12, 2018, 1:33 pm
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Part Number:TPS62821

Is there mechanical data and/or a suggested footprint available for the TPS62821? It's not included in the datasheet I have and I can't find it on the TI web pages for the part.

Thanks 

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Linux/AM3352: How to read and write SPI in user space

April 12, 2018, 1:34 pm
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Part Number:AM3352

Tool/software: Linux

I found there are some posts and documents showing how to read and write through /dev/spidev. 

Is there another way to read, write and config SPI  , other than file descriptor?

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SN74LVC2G74: Transition times / using CLR, PRE inputs

April 12, 2018, 1:36 pm
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Part Number:SN74LVC2G74

Hi,

In section 6.3 - Recommended operating conditions, you specify that for Vcc=5V the "Input transition rise or fall time" should be dt/dV=5nS/V (MAX).

Meaning that slow transition might be problematic.

Which inputs does this specification refers to?
I'm asking cause later in the doc, you use an RC circuit on the CLR input presumably to set the output to a known value after the power up.

(At least this is what I intend to do with this input).

But such a circuit will likely violate the transition time spec.

Please elaborate.

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DP83867E: RGMII LINK issue with an Ethernet switch

April 12, 2018, 1:50 pm
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Part Number:DP83867E

Hi

I am using a DP83867E PHY on my custom FPGA board. If I connect my FPGA board to my PC directly, I am getting the throughput I wanted and things are looking fine on Wireshark. Only when I use a gigabit ethernet switch between my PC and custom FPGA board, I got lots of retransmissions on Wireshark and receive really low throughput. On PC side, I am running the iperf client with the same options (send data continuously for 10 seconds) in both cases, and FPGA firmware is exactly the same. The same throughput test I run on an Altera Dev Board (with a marvell 88e1111 PHY) was working fine with and without the ethernet switch. When I look into DP83867 Registers, I have the following register values.

Reg#With Ethernet SwitchWithout Ethernet Switchcomment
00000x11400x1140
00010x79690x796DLINK STATUS: Not established with the switch
00020x20000x2000
00030xA2310xA231
00040x01E10x01E1
00050xCDE10xCDE1
00060x006F0x006F
00070x20010x2001
00080x60010x6001
00090x03000x0300
000A0x38FF0x7C00
000D0x401F0x401F
000E0x00000x0000
000F0x30000x3000
00100x50480x5048
00110xBC020xBC02
00120x00000x0000
00130x1C440x1C00
00140x29C70x29C7
00150x00010x0000
00160x00000x0000
00170x00400x0040
00180x61500x6150
00190x44440x4444
001A0x00020x0002
001E0x00020x0002
001F0x00000x0000
00250x04000x0400
00310x10B00x10B0
00320x10D30x10D3
00330x00000x0000
00430x07A00x07A0
006E0x00000x0000
006F0x00000x0100
00710x00000x0000
00720x00000x0000
00860x00770x0077
00FE0xE7210xE721
01340x10000x1000
01350x00000x0000

LED_0  Strap pin (Mode 1)  ----- Mirrior Disabled and SGMII Disabled

LED_1 Strap Pin (Mode 1)  ----- ANEG_SEL is 0 and RGMII Clock Skew TX[2] is 0

LED_2 Strap Pin (Mode 1)  ----- RGMII Clock Skew TX[1] is 0 and RGMII Clock Skew TX[0] is 0

ANEG_DIS/EEE_DIS (RX_CTRL Mode 3) ----- I changed it from Mode 1 to Mode 3 because of this https://e2e.ti.com/support/interface/ethernet/f/903/p/490569/1789543 

CLK_SKEW_RX all open (Mode 1), as well as PHY Addreess (Mode 1)

My problem right now is that I can't get the throughput I wanted with the ethernet switch, I tried 3 different switches, with and without management interface, all having the same issue. As I mentioned earlier, the throughput test worked fine with and without ethernet switch on Altera Dev Board which has a different PHY chip. 

Thanks,

Shan Z

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TPS53647: Regulator Accuracy over industrial Temp Range

April 12, 2018, 1:53 pm
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Part Number:TPS53647

I looking at the data sheet, it is hard to pin down how accurate the regulator will be operating under our conditions.  We need to specify it’s accuracy from -40C to 85C.  The two applications are at 0.95V and 0.85V. 

Another question is if the regulator would be more accurate in VRM12.0 mode or VRM12.5 mode.  0.95V and 0.85V can both be obtained in either mode.

In order to be able to guarantee our ability to maintain the Xilinx +/-3% accuracy on the core voltage we are contemplating using a load line.  The accuracy of the regulator and the tolerance of the Xilinx core voltage constrain the amount of load line impedance that can be programmed.  If the regulator has 1% accuracy, then the max amount of load line impedance drop would be 1.5% leaving 0.5% margin at full load. 

 

 

 

We are also attempting to simulate/calculate how much bulk capacitance is needed to withstand a current step.  Analyzing our Xilinx power spreadsheet, for one of the Xilinx FPGAs a 35 A load step is calculated.  How can we simulate or calculate how much capacitance is needed.

 

With the OSR and USR functions, can these features be simulated in Webench?  Or in SPICE?

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Linux/AM5708: Is DRA74x the same as AM5708?

April 12, 2018, 1:55 pm
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Part Number:AM5708

Tool/software: Linux

I am bringing up a custom AM5708 board. In the linux kernel, I see AM5718 and AM5728 support, but nothing on AM5708.

There are DRA74X support (such as device tree structure).

Can I base my DTS on DRA74X?

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