↧
LMK03318: Lock Detect
↧
DS90CR485: Does the national semiconductor part has the same pin out as the TI part?
Part Number:DS90CR485
Hi,
My boards got populated with chips with the national semiconductor logo dated back to 01212, they are not functioning as I expected, I found the pin-out in the datasheet from national is different than the ti. Could you please confirm that the pin-out in the ti datasheet is correct for this part? It is very important for me to have the correct pin-out since I'm only using 16 of the inputs and 3 of the output channels.
Your help with this is greatly appreciated. I would like to place an order for the ti parts as soon as possible.
Thanks
Roberto
↧
↧
LM5069: Over current detection time and filtering
Part Number:LM5069
Hi!
I use a LM5069-2 in an application to limit power at startup and also to protect for over current. My connection is very similar to the one shown in the application note snva683.
According to datasheet the circuit breaker can activate if the voltage over R10 (Vin - Vsens) is over 80mV (assuming worst case, minimum).
I can't find any information about how long time the voltage over R10 must be over the threshold to activate the circuit breaker. Obviously a "long" time for say 1ms will activate it. But what if the pulse is only 1ns, 10ns, 100ns?
Question: How long time must the pulse be over the threshold to active the circuit breaker?
In my application I get some spikes in the current and hence voltage over R10 so maybe I need to filter it. In this case I consider to add a small serie resistor between R10 and Vin and R10 and Vsens, next to the input to the LM5069 Vin and Vsens pins (between pin 1 and 2) I can place a capacitor to make a low pass filter together with the serie resistors.
Question: Is it suitable to filter the input signal Vin-Vsens in this way for the LM5069 part?
Other ways to make it less sensitive to "noise" on R10?
Best regards
Joakim
↧
TMS320F28335: TMS320F28335
Part Number:TMS320F28335
Hello Sir
There are some issues regarding code generation using the experimenter kit. We are working on hardware implementation of multilevel inverters for which we require six PWM signals. We have simulated the same model and the pulses are of 50Hz when observed on SIMULINK scope. However, once we are flashing the .out file generated by the simulink on the controllers using code composer studio , the frequencies of the six pulses are reduced to very low values i.e merely 1-2 Hz when observed on DSO.
What may be the possible cause ? What changes do we need to make in order to get appropriate results?
Thanking you
↧
Is End of Life for TMS320C6455BGTZ2 shown on Mouser Site correct?
Part Number:TMS320C6455
Mouser shows DSP as EOL. This can not be confirmed anywhere else that I have found. Is there a notification or is this an erroneous entry on their site?
↧
↧
Linux/TMDXEVM8148: Cannot install syslink from a ramfs
Part Number:TMDXEVM8148
Tool/software: Linux
I have an 8148 EVM configured to boot Linux with syslink enabled. I am able to boot from an NFS, and run the syslink Helloworld example but when I create a ramfs there is an error syslink: relocation out of range.
The system in question does not have enough flash to load a file system. In addition, the method of loading the kernel image does not lend itself to having an initrd filesystem loaded separately from the kernel.
Is there a method of having the syslink.ko reside in a ramfs?
Doing some research I found that there are issues running .ko modules from ramfs. The following links go into detail why.
Modules get placed 16MiB below PAGE_OFFSET, and when you add another
~16MiB initramfs between them and the kernel symbols, you exceed the
offset range of the branch instruction.
It's possible to hack around this by placing the initramfs at the end of
the kernel image rather than at the beginning with the rest of the init
data. Something like the below should work, although you should also
probably take care of alignment and also have this section freed when
the rest of the init data is freed.
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..05ad361 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -46,7 +46,6 @@ SECTIONS
INIT_CALLS
CON_INITCALL
SECURITY_INITCALL
- INIT_RAM_FS
#ifndef CONFIG_XIP_KERNEL
__init_begin = _stext;
@@ -170,6 +169,11 @@ SECTIONS
_edata = .;
}
+
+ .initramfs : {
+ INIT_RAM_FS
+ }
+
_edata_loc = __data_loc + SIZEOF(.data);
#ifdef CONFIG_HAVE_TCM
I applied this patch and was able to install syslink.ko (modprobe syslink).
Loading modprobe syslink
SysLink version : 2.20.02.20
SysLink module created on Date:Feb 26 2018 Time:16:07:22
The load-hd-firmware script waits for syslinkipc_ProcMgr and syslinkipc_ClientNotifyMgr to respond. They never do. So even though the syslink.ko gets loaded the notifications are not seen.
Hopefully this issue has been resolved. I have done some searching and cannot find anything.
-steve
↧
UCD90160A: PMBus Address Resistors on EVM vs DS
Part Number:UCD90160A
For the UCD90SEC64EVM-650 module, it uses address set resistors not listed in the data sheet table.
R16 and R19 are set to address 101 (84.5k and 36.5k)
But the data sheet table indicates to use 90.9k and 41.2k to get address 101
Why is there a difference?
Thanks!
Russell
↧
TMS320C6746: Power Rails
Part Number:TMS320C6746
Hello,
- We are planning to use the C6746 DSP on a new board and I was wondering if there are any caveats to using different power rails for the different power groups. Specifically, I would like to use 2.75V for Power Group A (because of a UART requirement) but use 3.3V for the rest of the device. Is this a problem? Is there a power sequencing requirement if we use different rails for the different power groups?
- Looking at the power on sequencing (§5.3.1) of the datasheet, it seems that the only valid voltages for the IO supply groups are 1.8V and 3.3V. Can you confirm this is the case?
- Is there any work around that can enable use of a 2.75V rail?
Best,
Nadeem
↧
CC3200MOD: Pin connections
Part Number:CC3200MOD
I have been asked what pins the serial data will be on for the metal can CC3200. Not having found a pin diagram for the CC3200MOD I am using the "CC3101 EVB Launch Pad" schematic to try to begin to get a grasp on the methodology. I see from the "P2p Demo" SW that RED, YEL, GRN LEDs are on pins 9, 10, 11.
#define GPIO_LED1 9 // Red D7 P64 GP09
#define GPIO_LED2 10 // Yel D6 P1 GP10
#define GPIO_LED3 11 // Grn D5 P2 GP11
And likewise from the artwork on the CC3200LaunchXL board that's pin 64, pin 1, and pin 2 (but actually I think they mean pin 54).
That matches with the "CC3101 EVB Launch Pad" schematic.
But the "Serial WiFi" SW refers to the UART RX and TX being on pin 57 and pin 55. On the "CC3101 EVB Launch Pad" schematic those are both listed as GND???
PinMuxConfig(void)
{
// Enable Peripheral Clocks
MAP_PRCMPeripheralClkEnable(PRCM_UARTA0, PRCM_RUN_MODE_CLK);
// Configure PIN_55 for UART0 UART0_TX
MAP_PinTypeUART(PIN_55, PIN_MODE_3)
// Configure PIN_57 for UART0 UART0_RX
MAP_PinTypeUART(PIN_57, PIN_MODE_3);
}
I have not found pin definitions for the 54 contacts of the CC3200MOD (metal can). I need to know what pins on the Metal Can I need to connect to for the 3 LEDs as well as the UARTA0 Rx and TX. It would be good to know all pins definitions for the 54 metal can contacts so can connect VCC, GND, one GPIO output and the two crystals.
↧
↧
TMS570LS20216: BSDL File
Part Number:TMS570LS20216
Is the BSDL file available for the PGE package of the TMS570LS20216? I did not find it on the product page.
↧
wlconf to Set Value of Specified Element
Hi team,
I am trying to use wlconf to set the value of a specific element (in this case, the number of assembled 5GHz antenna) but it is not setting. Am I using this command incorrectly? I am trying to set it to 0 but it looks like it is not changing from 1.
root@am335x-evm:/usr/sbin/wlconf# ./wlconf -i wl18xx-conf-default.bin -s wl18xx.phy.number_of_assembled_ant5=0x00
root@am335x-evm:/usr/sbin/wlconf# ./wlconf -i wl18xx-conf-default.bin --get > wl18xx-conf-default.txt
root@am335x-evm:/usr/sbin/wlconf# grep wl18xx.phy.number_of_assembled_ant5 wl18xx-conf-default.txt
wl18xx.phy.number_of_assembled_ant5 = 0x01
Regards,
Akash Patel
↧
DRV8323: Current Sense amplifier question
Part Number:DRV8323
Motor gurus:
On the DRV8323S - does the DRV8323S use any of the current sense input/outputs for internal use? In other words - if one does not connect them up (and uses an external sensing scheme) - would it cause issues in the DRV8323 operation?
There does not appear to be any internal (i.e. to the control/fault scheme) connection... but I wanted to check to make sure.
The alternative would be to simply change to the DRV8320RS version.
Thanks!
↧
TSW40RF80EVM: FTDI drivers do not work with WINDOWS 10
Part Number:TSW40RF80EVM
Dear all,
one of my AA customer has issues with the GUI of the TSW40RF80 in WIN 10.
He has been successfully using TSW14J56 (rev B and D) and TSW40RF80EVM on windows 8.1 computer for months; now Ihe has to setup another test station and he has got a PC with win 10. He updated windows and downloaded/installed the latest TSW40RF40 GUI and the HSDC pro installers from the TI website.
Problem is, everything works for ~5 minutes, then it appears that the FTDI chips are disconnected.
Do you have any hint on this? he already tried some workarounds, but none of them worked:
- downloaded latest drivers (2.12.28) from ftdichip website
- used older ones (2.8.24) instead (you never know…)
- disabled the possibility to suspend the USB devices to save power (both in device manager and advanced power manager settings)
- disabled serial enumeration
- reduced serial port latency timer from 16 to 1 ms
- used the EVMs with and without a USB hub
The PC USB ports are 3.0: no 2.0 USB is available.
thanks,
Domenico
↧
↧
F28M35H52C: No stack?
Part Number:F28M35H52C
Hello.
I have to place some sections in RAM and in order to have the maximal amount of space there I started reducing other sections. As a test, I wanted to see how small the stack could be (still allowing the program to work fine) and, surprisingly I found that I could set it to 0x0 and the program still worked (and I had the same results that I had had with -stack=0x1000).
I frankly can not understand how this is possible. Could someone please give me an explanation?
The .map (.txt) file is attached.
(Please visit the site to view this file)
↧
DAC38RF84: PRBS test
Part Number:DAC38RF84
Dear all,
one of my AA is testing the DAC38RF84 with his FPGA. In order to test the link he wants to send a PRBS and check that it arrives in the right way.
From the DS it seems that the only way to check the results of a transmission is sampling the bit TESTPATT through the internal mux (ALARM pin).
Do yuo confirm it ? Is there any other simpler test ? For instance is there any register which contains that info ?
The designer were thinkong to use the error counter register present int the device, but it seems more related to a specific protocol IEE1500.
Regards,
Domenico
↧
RTOS/TM4C1294NCPDT: CRC header for TI-RTOS
Part Number:TM4C1294NCPDT
Tool/software:TI-RTOS
I want my boot loader to perform a CRC check for a compiled TI-RTOS application. The boot loader needs a header "stored immediately above the vector table and marked by the words 0xFF01FF02 and 0xFF03FF04". A simple solution is given in this post: e2e.ti.com/.../2000471
TI-RTOS projects don't have a startup_ccs.c file AFAIK. How do I edit the vector table?
Amit's instructions seems to contradict the boot loader's instruction. Amit says to put the header after the last table entry. The boot loader asks for the header to be above the table. Should the header be stored before or after the table, or does order not matter?
TivaWare supplies source code to make a program that adds a CRC to binaries, binpack. I didn't realize I need to make this header myself until binpack gave me an error "The input file contains no image info header at the top of the vector table!"
↧
NE555: Schematic for IR TX/RX on/off control
↧
↧
ADS1278: TDM mode sample rate limitation?
Part Number:ADS1278
I am collecting data from the ADS1278 in fixed position TDM mode. My receiver is configured to latch data on the rising edge of SCLK as the ADC should be shifting on the falling edge. Running acquisitions at 144kHz I am always seeing the MSB of DOUT1 equal to one and the remaining DOUT1 bits at expected values. Data from the other 7 channels looks correct. I do have DVDD set to 2V and IOVDD at 3.3V.
After looking closer at the datasheet trying to debug this I am starting to doubt that you can actually get 8 channels at 144kHz in TDM mode. According to the frame-sync timing specification the min CLK period in high speed mode is 27ns. If you assume 50% duty cycle on the clock that gives you 13.5ns. However the allowed DOUT MSB propagation delay can be up to 21ns. Assuming 8 channels at 24 bits and a period = 2 * propagation delay, the best you can guarantee is ~93kHz.
Can anybody confirm my suspicions that this part is sample rate limited in TDM mode or am I seeing something else?
↧
TPS3305: Electrical Connection for PowerPAD
Part Number:TPS3305
I couldn't found any statement in the datasheet about how to connect the PAD. Can I just leave it float or should I connect it to GND externally?
↧
LMK00301: Output signal discontinuity
Part Number:LMK00301
Hi team,
Below is the diagram of my customer's application.
The output signal of LMK00301 is LVPECL and the input signal of the CPLD is LVDS.
Customer use the CPLD to monitor the output clock of the LMK00301, and we found when the temperature is high, there occur the problem of frequency shift.
And we also get the input signal of the CPLD.
Could you help me to check the matching network between the LMK00301 and CPLD and give your comment to the problem.
Lacey
Thanks a lot
↧