Part Number:BEAGLEBK
Tool/software: Linux
We have a custom board based on some TDM codecs connecting to McASP0 on the BeagleBone black. 8 TDM channels, with setting CBS CFS & the on-board McASP 24.576MHz clock for MCLK. This MCLK is shared to board above too.
I have a ti-rt 4.14 kernel with my custom driver running jackd2 with a very low period & high priority.
Have put some printks into the kernel, and I get this repeated error caused by jack xruns, restarting the soundcard.
I have patched mcasp driver so that when GBLCTL is written to, GBLCTL is readback as HERE.
This repeats over & over while jack's softmode is enabled. This only happens with really tiny period values, with 256 and above it trys to restart the card once or twice.
[ 748.951772] AUDIOTEST davinci_mcasp_start stream: 0
[ 748.956704] AUDIOTEST mcasp_start_tx
[ 748.960317] AUDIOTEST davinci_mcasp_start stream: 1
[ 748.965219] AUDIOTEST mcasp_start_rx
[ 748.969932] AUDIOTEST GBLCTL write error reg: 96 val: 1
[ 748.976214] AUDIOTEST davinci_mcasp_stop stream: 0
[ 748.976420] davinci-mcasp 48038000.mcasp: Transmit buffer underflow
[ 748.987335] AUDIOTEST mcasp_stop_tx
[ 748.990847] AUDIOTEST davinci_mcasp_stop stream: 1
[ 748.995659] AUDIOTEST mcasp_stop_rx
[ 748.999212] davinci-mcasp 48038000.mcasp: unhandled rx event.
rxstat: 0x00000104
So first when mcasp_start_rx is called, it tries to set GBLCTL.RCLKRST and fails.
Then, when transfer occurs, the processor sets RSTAT.RCKFAIL as it has failed.
This means RCLK is failing to turn on. Which is strange as TCLK is OK.
The MCLK is onboard, and is enabled when board is turned on.
The priority of the McASP interrupts is 95, jackd is 90. Do I need to set any DMA interrupts?
DTS snippets:
pinctrl-single,pins = <
+ /* P9_25 McASP0 Transmit Master Clock (MCLK) */
+ AM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE0)
+
+ /* P9_28 McASP0 Serial Data 2 (OUT) (DAC_SDATA) */
+ AM33XX_IOPAD(0x99c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)
+
+ /* P9_29 McASP0 Transmit Frame Sync (LRCLK) */
+ AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLUP | MUX_MODE0)
+
+ /* P9_30 McASP0 Serial Data 0 (IN) (ADC_SDATA) */
+ AM33XX_IOPAD(0x998, PIN_INPUT_PULLUP | MUX_MODE0)
+
+ /* P9_31 McASP0 Transmit Bit Clock (BCLK) */
+ AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+
+ /* Y4 MCLK oscillator disable (active-low) */
+ AM33XX_IOPAD(0x86c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)
+ >;
+&mcasp0 {
+ op-mode = <0>;
+ tdm-slots = <8>;
+ serial-dir = <
+ 2 0 1 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ >;
+ tx-num-evt = <1>;
+ rx-num-evt = <1>;
+};
Driver snippets:
snd_soc_dai_set_sysclk(cpu_dai, MCASP_CLK_HCLK_AHCLK, sysclk, SND_SOC_CLOCK_IN);
snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
snd_soc_dai_set_tdm_slot(cpu_dai, 0xFF, 0xFF, 8, 32);
What can cause this behavior with the RX Clock?