Part Number:TM4C1294NCPDT
Tool/software: Code Composer Studio
Hello,
I am trying to run an example code for the TM4C1294NCPDT to ensure that I can communicate with an ADS7142 via I2C. I receive "unresolved symbol" errors for a number of functions in the code. I have all of my includes in the workspace so I do not understand how to fix this linker error with the compiler. I am running version 7.4.0.00015. Here is a snippet of my errors:
Part Number:CC3220S-LAUNCHXL
Hello,
I used cloud_ota example to successfully download oob example from dropbox into cc3220s. Now, when I connect cc3220s, it starts oob. I assume cloud_ota has been overwritten.
How can I keep OTA feature "alive" after downloading the oob example? I want to still be able to press a button and check for updates in dropbox. This doesn't seem to work after downloading oob example.
Thanks,
David
Part Number:TUSB8041A
Hello,
I am trying to use the TUSB8041A but when I connect my computer to the upstream port my computer says that the USB device is unrecognizable. I am thinking that the problem is with the power supply start up and power on reset timing. In the datasheet on page 34 it states that
"The 1 µF capacitor on the GRSTN pin can only be used if the VDD11 supply is stable before the VDD33 supply. The depending on the supply ramp of the two supplies the capacitor may have to be adjusted."
The datasheet also states on page 11, footnote 1:
"An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz."
I am supplying the 3.3V with a linear regulator and the 1.1V with a buck converter, both off a 5V buck. Therefore the 3.3V is stable before the 1.1V voltage is stable. See below the transient supply voltage for 1.1V (yellow) and 3.3V (Blue). The 3.3V is stable about 1ms before the 1.1V.
Now adding the GRSTz pin on channel 3 as the pink signal. Here you can see that the reset signal is de-asserted with a long RC ramp. From the datasheet I believe once the voltage gets to 2V then the reset is de-asserted. In which case that point happens about 15ms after both supplies are stable. Could you please tell me if I am mis-reading the datasheet and if the reset may be the reason why I am not able to connect to the upstream port?
Thanks!
Erik
Part Number:ADS127L01
Hiya,
I've been having conversations with colleagues about the best (lowest noise?) ways to connect AGND to DGND on primarily "analog" devices such as the ADS127L01.
The datasheet says this:
"The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this split is not necessary. Place analog signals over the analog plane and digital signals over the digital plane. As a final step in the layout, completely remove the split between the analog and digital grounds. If ground plane separation is necessary, make the connection between AGND and DGND as close to the ADC as possible."
Fair enough, I've read this other places as well, that on an "analog" chip with digital I/O, connect AGND and DGND together as close as possible to the chip on the "analog GND" plane.
BUT... The ADS127L01EVM doesn't appear take this advice. See Figure 19 of: www.ti.com/.../sbau261b.pdf, there are two planes, one connected to DGND, and a separate one for AGND under the ADS127L01. They appear to be shorted together through the board using the plane on the bottom and the GND testpoints which are not near the ADSL127L01. So, why did eval board layout not the datasheet advice? It is not a single physical plane and it is not connected close to the ADC (or am I reading the eval board incorrectly?).
Thanks!
Part Number:TL084
Dear all,
I have a device that I measure its IV curve, this device's working voltage range is from -3 to 3 V, and in order to read the IV data I'm using the ADS1115, so I have to convert the device's input and output voltages to a unipolar signal from 0 to 3 V and to do this I'm using TL084CN , when I connect this opamp to the first terminal of the device the signal is converted successfully but when I do the same in the other terminal of the device where there is a resistor connected to measure the current, the negative side of the input signal of the opamp disappears and I see only the positive side, is that because of the common voltage range of the opamp? could someone explain this for me, the power supply of the opamp is -5 V and 5 V. The same thing happens when I connect LM324 opamp.
The circuit schematic is attached.
Thank you,
Part Number:TPS51116
Hello,
One of my customers is currently use a 100uF 10% tolerance low-ESR ceramic cap on C6 in their application. However, the cap they are using is going obsolete and they only have have options for a 100uF 20% tolerance cap.
Can we get confirmation of what this will effect (if anything)... should this be OK?
The current design: Pin 20 (LL) to 2.2uH 20% tolerance 8A (L1) in series with a 100uF 20% tolerance 6.3V (C6)
Part Number:TMS320F280049
In the F280049 Data Manual Electrical Characteristics, the The VOH parameter shows a min of VDDIO-0.2V for the test condition of IOH=-100uA.
Using the IBIS model, this does not seem to match (shows around VDDIO-0.34V).
Please confirm which is correct, i.e. min High-Level voltage with output current of 100uA.
Can someone please validate the IV curve data in the IBIS model (reference BCF3385D_DRIVER_3P3)?
Thanks,
Eric
Part Number:TMS320F28075
Tool/software: Code Composer Studio
I'm not sure what happened.
I have a bootloader that starts on the processor which jumps to a main program.
This has been working for a long time.
Suddenly, my boot loader will not start on power up or after a reboot. From the debugger, I can see that it seems to get stuck after a reboot at 0x3fee00 then goes to 0x3fee04 then loops back to 0x3fee00.
My OTP has never been written and still appears to be the original values (all ones) (this is from both Z1 and Z2). My boot pins GPIO72 and GPIO84 are both high (they have a 100K pull up on them).
I can't seem to get the debugger to attach with the bootROM source code, one reason being I can't find the old compiler anymore (can you give me a link to the legacy compilers page, I can't seem to find it anymore?).
The boot loader has not changed and it's starting up and working fine on another board with the same processor. I have not had the chance to see if if it works on another board just yet.
Can you tell me why this is getting stuck and jumping to flash or help me connect and debug what might be happening in the debugger?
Part Number:EK-TM4C123GXL
Tool/software: TI C/C++ Compiler
Hi,
I am trying to run the grlib_demo with LCD Booster Pack.
Since the Display was not working so i was searching around to see what is the issue and how to fix. Based on this post, I tried the modification and flash the device. Since then it has stopped communicating any more.
Here is the snapshot of the code I introduced (From Line #1035 to 1044) and the error is shown as well.
Please advise.
Thanks
Part Number:AWR1642
Hello;
Looking at the release notes for the latest mmwave SDK release, v1.2, there's a mention of "Bug MMWSDK-1058".
C:\ti\mmwave_sdk_01_02_00_05\docs\mmwave_sdk_release_notes.pdf
The bug is described as:
"mmwDemo: Intermittent mmwave control error received when switching between profiles"
Is there any further information on this bug and exactly what code had to be updated to resolve this issue? Due to the current state of our product, it's not a simple task to update SDK versions, but this particular bug is of concern to us.
Clicking on the "MMWSDK-1058" link brings us here: https://jira.itg.ti.com/browse/MMWSDK-1058
However, the link is broken.
Thanks,
Erik
Part Number:TAS6424Q1EVM
Hi TI,
I have my PCB up and running with the CPU and TAS6424 chip. However I constantly am getting a Global Fault of 0x10 which is a "clocking error".
I'm new to I2S and am learning about it. I can product a clean 44.2Khz FSYNC(LRCLK) and associated SCLK signals along with SDIN, all seems
fine. I can tune the CPU clock to get to the 44.1Khz that is required if needed. Not sure what the error % tolerance needs to be, will consult the
datasheets for that.
However producing the 11,289,600 Hz MCLK with this CPU is a problem. So, I am thinking of simply using a crystal oscillator device that
produces the TTL (3.3v) frequency for the TAS6424 chip. Does this sound ok to do? As I understand the MCLK rise/fall or phase does not have to
be related to the other I2S signals, just there at the frequency with about 50% duty cycle, correct?
A side note, the waveforms shown in the data sheet do not show MCLK in the graphics, and not clear if it is required for I2S and/or TDM8 formats?
I guess that also the "left justified" and "right justified", "TDM8" and "I2S" are all different formats, the left/right justified not being I2S format though,
I was pretty confused if they are I2S or simply similar to SPI type signals.
I assume, as described, when I feed the correct relationship of these four signals to the IC it will clear the error and restore the channel state report
register to what is in the channel state setting register (i.e. play mode)?
I may have FSYNC,SCLK,SDIN correct now, but with out MCLK at the correct frequency I will not get any output, that is what I'm working on to
resolve in order to get actual output from the device.
Thanks for any help or advice gang,
Marc Y.
Part Number:ADC12DJ3200
HI,
I'm now working on a JESD204B core implementation on an XILINX FPGA interfacing an ADC12DJ3200。In the RX end ,I find the data arrival time is varying within a LMFC period.For example ,when set K =4,F=8, sample rate = 4.4GS/S,the LMFC period is 290ns,the data arrival time vary from 410 to 430ns. If I chane K=32,the variation is between 400 to 600ns .It seems I can not get a determinstic latency.
Thanks in advance.
Part Number:SN65DSI85EVM
Hello,
I am looking for the MIPI DSI to LVDS bridge evaluation board - SN65DSI85EVM OrCAD .dsn files. My email address is andy.kulikyan@axiomtek.com
Can you please email them to me?
Thanks a lot.
Hi, Team
Currently we have SN75LVPE801 as PCIe / SAS re-driver in stock, now our application is pure USB 3.0 data transmission through type-C connector, without DP/ALT mode
There is a mux (HD3SS3212) placed between type-C connector and USB Host processor for USB cable orientation selection, and another PD chip for power delivery negotiation.
What we need is the re-diver / equalizer to improve the signal integrity for USB TX/RX.
May I know if the re-driver SN75LVPE801 is suitable for USB 3.0 5Gbps application please?
Thanks
Chenglin WU
Part Number:TM4C1294KCPDT
I'm using LMFlash to perform an Ethernet firmware update on a custom board which uses the TM4C1294KCPDT microcontroller. This issue also affects our custom boards which use the LM3S9D96, as well as the evaluation board EK-TM4C1294XL. When I click Program in LMFlash, the status bar indicates "Attempting to connect..." and never progresses. This issue also affects the eflash utility (although I don't know if you can call it a bug in that case, since eflash has no option to select the local interface to use).
I have observed (using Wireshark) that when more than one network interface is present on the system, LMFlash may send the magic packet over an interface different to the one it was told to use. I would speculate that it uses whichever adapter enumerates first in a call to the Winsock function gethostbyname(), since this is what eflash does.
A workaround is available - by disabling all network adapters in the Windows control panel (except the interface we are using), LMFlash will send the magic packet to the correct interface.
I have also observed that by sending the magic packet myself (using scapy) whilst LMFlash is in the "Attempting to connect..." state, I can trigger the target to send the BOOTP request. Once this is done LMFlash sends a BOOTP reply and the rest of the firmware update process completes successfully.
We require a fix for this bug since it complicates our support requirements (less technically-minded people need to be able to operate the software reliably).
Part Number:DS92LV2422
Hello,
Our customer use the DS92LV2422, have a question.
The customer use the DS92LV2422 with 75MHz parallel clock.
The DS92LV2422 receive a 1.05GHz serial data and internal PLL circuit locked 75MHz.
How about the maximum internal clock for read serial data? Is it 1.05GHz ? or 2.1GHz?
Best Regards,
Naoki Aoyama
Part Number:XIO3130
Hello,
Please advise regarding XIO3130 below,
My System configration:
RC(RootComplexPCIe)---XIO3130 UP(upstream)port
EP0 (EndPointPCIe Device)---XIO3130 DN1(downsteam)port
EP1 (EndPointPCIe Device)---XIO3130 DN2(downsteam)port
Is it possible to communicate bitween EP0 and EP1 directly?
For examle, EP0's DMAC(PCIe master) directly access(read/write) to EP1's
memory(PCIe slave).
Part Number:BQ27520-G4
Hello,
It is my understanding that there are two steps:
Step 1: If voltage is greater than charge voltage – taper voltage, then it goes to the next step 2.
Step 2: If current is less than taper current, then charge is completed.
The settings in the fuel gauge are charge voltage = 4.3V, taper voltage = 0.13V, and taper current = 300mA. The steps become:
Step 1. If voltage > 4.17V, then it goes to step 2
Step 2.If current < 300mA, then charge is completed
Can you help comment on the following scenarios?
Thank you,
Ryan B.
Part Number:LMS3655
Hi,
I need a negative converter design used to function as a preregulator for an negative regulator/LDO in a power supply design.
I am using a LLC converter/transformer with center-tapped secondary to step the voltage down to +/- 24V.
The power supply has Plus/minus outputs.
The positive voltage side is easy.
However for the negative side:
I can simulation a typical buck converter in a feedback loop around the negative regulator/LDO using ground/center tap acting as a floating voltage sense and with the negative supply (-24V)
acting as ground. So I am converting to a lower voltage (-3V to -24V) relative to ground.
I know this is very sensitive to the negative power rail @ -24V.
Can someone suggest a better solution?
