Part Number:TMS320F28379D
Hi,
I updated the LAB7 example in C28xx experimenter Kit to include the ADCB0, ADCC0, and ADCD0 in addition to ADCA0. when I debug the code and run it on my experimenter kit, ADCC0 is not working while the other adc work probably and I see the conversion result in the memory browser or expression window and I can plot the conversion outcome. I tried to change the ADCC channel but still, I don't get any conversion result and the output buffer still null.
Below is the ADC file as well as the ISR interrupt for the ADCC:
voidInitAdca(void)
{
asm(" EALLOW"); // Enable EALLOW protected register access
//--- Reset the ADC. This is good programming practice.
DevCfgRegs.SOFTPRES13.bit.ADC_A = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_A = 0; // ADC is released from reset
DevCfgRegs.SOFTPRES13.bit.ADC_B = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_B = 0; // ADC is released from reset
DevCfgRegs.SOFTPRES13.bit.ADC_C = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_C = 0; // ADC is released from reset
DevCfgRegs.SOFTPRES13.bit.ADC_D = 1; // ADC is reset
DevCfgRegs.SOFTPRES13.bit.ADC_D = 0; // ADC is released from reset
//--- Configure the ADC base registers
AdcaRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
AdcbRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
AdccRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
AdcdRegs.ADCCTL1.all = 0x0004; // Main ADC configuration
// bit 15-14 00: reserved
// bit 13 0: ADCBSY, ADC busy, read-only
// bit 12 0: reserved
// bit 11-8 0's: ADCBSYCHN, ADC busy channel, read-only
// bit 7 0: ADCPWDNZ, ADC power down, 0=powered down, 1=powered up
// bit 6-3 0000: reserved
// bit 2 1: INTPULSEPOS, INT pulse generation, 0=start of conversion, 1=end of conversion
// bit 1-0 00: reserved
AdcaRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
AdcbRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
AdccRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
AdcdRegs.ADCCTL2.all = 0x0006; // ADC clock configuration
// bit 15-8 0's: reserved
// bit 7 0: SIGNALMODE, configured by AdcSetMode() below to get calibration correct
// bit 6 0: RESOLUTION, configured by AdcSetMode() below to get calibration correct
// bit 5-4 00: reserved
// bit 3-0 0110: PRESCALE, ADC clock prescaler. 0110=CPUCLK/4, Hence ADC Clock = SYSCLK / 4 = 200 MHz/4 = 50MHz
AdcaRegs.ADCBURSTCTL.all = 0x0000;
AdcbRegs.ADCBURSTCTL.all = 0x0000;
AdccRegs.ADCBURSTCTL.all = 0x0000;
AdcdRegs.ADCBURSTCTL.all = 0x0000;
// bit 15 0: BURSTEN, 0=burst mode disabled, 1=burst mode enabled
// bit 14-12 000: reserved
// bit 11-8 0000: BURSTSIZE, 0=1 SOC converted (don't care)
// bit 7-6 00: reserved
// bit 5-0 000000: BURSTTRIGSEL, 00=software only (don't care)
//--- Call AdcSetMode() to configure the resolution and signal mode.
// This also performs the correct ADC calibration for the configured mode.
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
//--- SOC0 configuration
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel ADCINA0 (Ch. 0)
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdcaRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//---- SOC1 configuration for ADCA2
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdcaRegs.ADCSOC1CTL.bit.CHSEL = 2; // Convert channel ADCINA2 (Ch. 2)
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdcaRegs.ADCINTSOCSEL1.bit.SOC1 = 0; // No ADC interrupt triggers SOC1 (TRIGSEL field determines trigger)
AdcaRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- SOC0 configuration For ADC B
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel ADCINB0 (Ch. 0)
AdcbRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdcbRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)
AdcbRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- SOC0 configuration For ADC C
AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdccRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel ADCINB0 (Ch. 0)
AdccRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdccRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)
AdccRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- SOC0 configuration For ADC D
AdcdRegs.ADCSOC0CTL.bit.TRIGSEL = 7; // Trigger using ePWM2-ADCSOCA
AdcdRegs.ADCSOC0CTL.bit.CHSEL = 0; // Convert channel ADCINB0 (Ch. 0)
AdcdRegs.ADCSOC0CTL.bit.ACQPS = 19; // Acquisition window set to (19+1)=20 cycles (100 ns with 200 MHz SYSCLK)
AdcdRegs.ADCINTSOCSEL1.bit.SOC0 = 0; // No ADC interrupt triggers SOC0 (TRIGSEL field determines trigger)
AdcdRegs.ADCSOCPRICTL.bit.SOCPRIORITY = 0; // All SOCs handled in round-robin mode
//--- ADCA1 interrupt configuration
AdcaRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC0 triggers the interrupt
//--- ADCB1 interrupt configuration
AdcbRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state
AdcbRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdcbRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC0 triggers the interrupt
//--- ADCC1 interrupt configuration
AdccRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC0 triggers the interrupt
//--- ADCD1 interrupt configuration
AdcdRegs.ADCINTSEL1N2.bit.INT1CONT = 1; // Interrupt pulses regardless of flag state
AdcdRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable the interrupt in the ADC
AdcdRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // EOC0 triggers the interrupt
//--- Enable the ADC interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable ADCA1 interrupt in PIE group 1
PieCtrlRegs.PIEIER1.bit.INTx2 = 1; // Enable ADCB1 interrupt in PIE group 1
PieCtrlRegs.PIEIER1.bit.INTx3 = 1; // Enable ADCC1 interrupt in PIE group 1
PieCtrlRegs.PIEIER1.bit.INTx6 = 1; // Enable ADCD1 interrupt in PIE group 1
IER |= 0x0001; // Enable INT1 in IER to enable PIE group
//--- Finish up
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1; // Power up the ADC
DelayUs(1000); // Wait 1 ms after power-up before using the ADC
asm(" EDIS"); // Disable EALLOW protected register access
} // end InitAdc()
//--- end of file -----------------------
While the ISR code is:
interruptvoidADCC1_ISR(void) // PIE1.3 @ 0x000D44 ADC-C interrupt #1
{
staticUint16 *AdcBufPtr2 = AdcBuf2; // Pointer to buffer
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group
//--- Manage the ADC registers
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear ADCINT1 flag
//--- Read the ADC result
*AdcBufPtr2++ = AdccResultRegs.ADCRESULT3; // Read the result
//--- Brute-force the circular buffer
if( AdcBufPtr2 == (AdcBuf2 + ADC_BUF_LEN) )
{
AdcBufPtr2 = AdcBuf2; // Rewind the pointer to beginning
}
}
I really appreciate any help
Regards
