Hello,
Regarding DS100KR401: Is there a maximum length that the repeater can support?
For example, channel lengths may be set something like this: Processor<-25inches->repeater<-25inches->switch processor. Will this be an issue?
Thank you.
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DS100KR401: Is there a maximum length that the repeater can support?
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C plus plus link error with mathlib
Hello,
I am using C++ language with C66x CGTv7.4.4.
When I compile the simplest Mathlib(mathlib_c66x_3_1_0_0) sample code, the linker error always occurs.
I really can not understand the causing to complete build.
Could you let me know the advise to avoid this?
I would like to attach the sample code:
(Please visit the site to view this file)
Sample code:
====
#include <C:\ti\mathlib_c66x_3_1_0_0\packages\ti\mathlib\src\divdp\c66\divdp.h>
double a=100.0, b=20.0, c;
int main(void) {
c = divdp(a, b);
return 0;
}
Error message:
====
Best regards, RY
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balance and Unbalanced outputs tlv320aic3254
I want to add buffer stages to the output of this chip so that I have both unbalanced and balanced mono outputs. These can be active at the same time, but I see three ways of doing this:
1. Use one line out and create a unbalanced to balanced circuit.
2. Use both line outs and create a balanced to unbalanced circuit.
3. Use one line out for unbalanced out and the Headphone outs for balanced. Not sure if this is do-able, but it would give me the most flexibility. Can I just connect a high impedance input to these?
This is a single supply design.
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SN74LVC244A buffer spec
I don’t see a maximum toggle rate called out. Should we calculate the rate from the propagation delays?
At 1.8V over -40 to +85, tpd = 10.4nS = tplh=tphl, fmax = 10.4nsx2= 20.8ns = 48mHz. (30pF load)
That would end up being a triangle/sawtooth though.
Any guidance is appreciated.
Regards,
Aaron
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TRF7970ABP "program make is not found in path" error
hello,
iam using a trf7970a nfc booster pack on the msp430g2553 .when i execute the demo project i get an error saying "Program make is not found in PATH"..iam new to nfc ..please provide an answer to this error...thanks in advance..iam including the snapshot of the error
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TI-RTOS PROJECT CAN NOT BE BUILT
Hello,
When i am trying to import or creating a new TI-RTOS project, the below warning appears;
After i click on "OK" and try to build the project, firstly i receive some path related errors like "cannot open source file xdc/std.h". I added the necessary paths (but i think i am not supposed to do, because i imported the project from TI Explorer examples), and get rid of the path related errors, than some other errors occured which i copied below;
-- cannot find file "./configPkg/linker.cmd"
-- Cannot open command file './configPkg/compiler.opt
Could someone help please ?
CCS version 5.5
TI_RTOS version 1.21.00.09
XDC version 3.25.04.88
Thanks.
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Linux boot freezing on custom board
I'm working on porting Linux to a custom board based on the am335x EVM. I'm getting a problem where the booting of the kernel freezes at about the statement "INIT: version 2.88 booting". I've seen it get slightly past this or freeze slightly before this.
The hardware is custom but designed directly from the EVM and keeps the following components from the EVM:
microSD card (same connections as EVM)
512MB DDR2 (same connections as EVM)
256kb EEPROM (same connections as EVM)
RS-232 Serial Port (same connections as EVM)
WiFi Radio (not identical connections as EVM)
Other specs:
No RTC clock, system oscillator frequency matches EVM.
It also adds a couple SPI connected peripherals.
I'm attempting to boot from SD card using the EVM files. I've modified them slightly to remove unused peripherals and force it to look like the EVM board despite not having that data in the EEPROM. The EVM will boot (with a few warnings about the removed peripheral modifications), however, the custom board freezes.
Any help would be appreciated! I can provide any information necessary.
Thanks,
Alex
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Controlling stack with HCI commands
Few questions about new stack:
1)When I use hostTestRelase-project as peripheral device some standard HCI commands are not working. BUT...when I comment out eventHandlers (in hosttestrelase project) of upper level of the stack (L2CAP, GAP, GATT...) device seem to work like controller stack with standard HCI interface. Is it possible to use stack like this? What could happen?
2) Is gatt database off chip function working?
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LMH1983 TOF Jump
Hello
I use the LMH1983 to synchronize to the reference input video which in turn generates TOFs which are used by the output video blocks to frame synchronize.
However, when we switch between two different reference inputs, I see that the TOF of the LMH1983 jumps to a new phase location and drift ,which causes the video output blocks to jump too, causing a glitch.
Is there a way to switch to a new reference without making the LMH1983 TOF jump and then slowly drift lock to the new reference? I am not worried about the lock signal but just the TOF jump. All I am trying to do is keep the LMH1983 TOF to be stable and drift lock to a new reference during reference switch.
I tried to switch to never align and then go to Holdover or freerun mode and then switch the references. But, I still see the TOF jump in the LMH1983.
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RF430F5978 Compatibility?
Could the microreader2 talk to the LF radio in the RF430? Also the datasheet mentions that the RFID transponder is a TMS37206? I suppose this would have similar functionalities as the TMS37157?
Also on a somewhat related topic, will the PaLFI transponder work with the S251B (RI-STU-251B)? If so, could you tell us or have documentation on how to read the PaLFI transponder?
Thanks
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TLV320DAC3100 problem on custom board
Dear ALL,
ON my board I am using TLV320DAC3100, I am providing 12.37MHz MCLK input, and clock configuration is PLL source=MCLK and CODEC clk_in source= PLL clk. I tried making DAC as I2S master but not getting any clock also not able to generate beep too. Also making DAC as I2S slave also not working, in this case i probed and found clocks and data is present.please find my i2c sequence below.
Page-0
------
i2cset -f -y 2 0x18 0x00 0x00
i2cset -f -y 2 0x18 0x01 0x01
Clock configuration:12.3751Mhz, 48k
------------------------------------
//PLL_clkin = MCLK,codec_clkin = PLL_CLK
i2cset -f -y 2 0x18 0x04 0x03
//pll power-up P=1, R=1
i2cset -f -y 2 0x18 0x05 0x91
//J=7
i2cset -f -y 2 0x18 0x06 0x07s
//D=4472: D-MSB=0x11 D-LSB=0x78
i2cset -f -y 2 0x18 0x07 0x11
i2cset -f -y 2 0x18 0x08 0x78
//ndac power-up, NDAC=3
i2cset -f -y 2 0x18 0x0b 0x83
//mdac power-up, MDAC=5
i2cset -f -y 2 0x18 0x0c 0x85s
//DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
i2cset -f -y 2 0x18 0x0d 0x00
i2cset -f -y 2 0x18 0x0e 0x80
i2cset -f -y 2 0x18 0x1b 0x00 //i2s, 16bit, slave
i2cset -f -y 2 0x18 0x3c 0x0B //PRB_P11 for playback
i2cset -f -y 2 0x18 0x3c 0x19 //PRB_P25 -for beep
i2cset -f -y 2 0x18 0x00 0x08
i2cset -f -y 2 0x18 0x01 0x04
i2cset -f -y 2 0x18 0x00 0x00
Page-1
------
i2cset -f -y 2 0x18 0x00 0x01
i2cset -f -y 2 0x18 0x1F 0x04
i2cset -f -y 2 0x18 0x21 0x4E
i2cset -f -y 2 0x18 0x23 0x44
i2cset -f -y 2 0x18 0x28 0x06
i2cset -f -y 2 0x18 0x29 0x06
i2cset -f -y 2 0x18 0x1F 0xC2
i2cset -f -y 2 0x18 0x2a 0x1c
i2cset -f -y 2 0x18 0x20 0x86
i2cset -f -y 2 0x18 0x24 0x92
i2cset -f -y 2 0x18 0x25 0x92
i2cset -f -y 2 0x18 0x26 0x92
page-0
-------
i2cset -f -y 2 0x18 0x00 0x00
i2cset -f -y 2 0x18 0x44 0x00
i2cset -f -y 2 0x18 0x42 0xD4
i2cset -f -y 2 0x18 0x41 0xD4
i2cset -f -y 2 0x18 0x3f 0xD4
i2cset -f -y 2 0x18 0x40 0x00
AUDIO BEEP GENERATION:
======================
i2cset -f -y 2 0x18 0x00 0x00
i2cset -f -y 2 0x18 0x47 0x00
i2cset -f -y 2 0x18 0x48 0x80
i2cset -f -y 2 0x18 0x49 0x00
i2cset -f -y 2 0x18 0x4A 0x56
i2cset -f -y 2 0x18 0x4B 0x22
i2cset -f -y 2 0x18 0x4C 0x09
i2cset -f -y 2 0x18 0x4D 0x1C
i2cset -f -y 2 0x18 0x4E 0x7F
i2cset -f -y 2 0x18 0x4F 0xAB
Any support on this issue or any sequence I can test to find if there is any problem with DAC
Thanks and Regards
Vivek
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Removing the delay introduced by the for loop inside the ADC sampling
I am using the CC430F5137 with the CCS5.5.Here, each ADC sample is obtained at a rate of 500Hz(2ms) so taking the samples obtained in 1 sec duration(each sample in 2ms so 2ms*500ADC samples=1 sec) and counting the number of transitions of 0 to 2 and transitions from 2 to 0 in the obtained 1sec samples.
Before using the for loop condition it is working fine as it was displaying the seconds count after every second of the real clock on the terminal.
But the for loop of counting the transitions is introducing a delay of around 3secs which was verified with the terminal window output by displaying the seconds count after every second.
After the first seconds count is displayed on terminal (like 01)it is showing nothing(just the cursor is blinking) for the next 3secs and after this 3 secs it is again showing the seconds count (like 02 secs)on the terminal.
Again for the next 3secs it is not showing anything on the terminal and after this 3secs it is displaying the next seconds count(03) and it is continuing like this.
The baud rate used for displaying each sample of ADC on the terminal is 115200.
Can someone explain how to remove this delay of around 3 sec’s to get seconds displayed after each second.
void main( void )
{
UART_init();
while (1)
{
//conv1(oldest);
ADC12CTL0 |= ADC12SC;//start ADC conversion(after 2ms of timer job)
__bis_SR_register(CPUOFF + GIE);//CPU OFF mode
}
}
#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR(void)
{
if (oldest == 499)
{
for (t=0; t<oldest;t++)
{
present=results[t];
present=(present*2.5)/4095;
if(t>0)
{
if (next==0 && present==2 )
{
up_count=up_count+1;
}
if(next==2 && present==0 )
{
down_count=down_count+1;
}
}
t=t+1;
next=results[t];
next=(next*2.5)/4095;
if (present==0 && next==2)
{
up_count=up_count+1;
}
if(present==2 && next==0)
{
down_count=down_count+1;
}
}
if (secs<10)
{
secs=secs+1;
uart_transmit(secs);
}
else
{
sec1=sec1+1;
secs=sec1+secs;
uart_transmit(secs);
secs=0;
}
oldest=0;
}
else
{
oldest=oldest+1;
}
result=ADC12MEM0;//Store ADC12MEM0 value to result(variable)
results[oldest]=result;
__bic_SR_register_on_exit(CPUOFF);
}
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problems of LMK04816
SIR：
I use LMK04816 in my design for the first time in my design. I encounter some problems that is puzzled me.
I reset the device through the configure of register R0, then I configure register R0 to R31 according to my design. After that, clockout0, clockout2, clockout6, clockout8, clockout10 produce output clock in 250Mhz, which is coincident with my design. But:
I configure LD_MUX R[31:27]= 3, which means Status_LD pin is connected to “PLL1 & PLL2 DLD”. I configure LD_TYPE R[26:24]=3, which means the Status_LD pin is Output(push-pull).
But the Status_LD pin is not active. What is the possible reason for this problem?
When I test the output clock using oscilloscope, I find the 5 output clocks are not in the same level standard. In fact, I configure all the 5 clocks in the same level standard(1600mV LVPECL). Like, the peek-to-peek value for one signal of the differential of clockout2 and clockout6 is about 500mV, while the peek-to-peek value for clockout8 and clock10 is about 900mV. But for clockout0, one signal of the differential clock has a peek-to-peek value of about 900mV, the other has a value of 160mV. What’s the possible reason for this problem?
Regards
Thanks
Jacky
2014-01-18
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PTxx Connect Inhibit pin on three modules
I have there modules that I want to inhibit at the same time. I have two PTH08080W and one PTH080260. Can I connect the Inhibit pins together and control with one FET?
Thank you,
Jose
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AFE5809 Clock management
Hi,
I am using 8 chips of AFE5809 to communicate with one xilinx FPAG .each chips of AFE5809 has 2 out put clocks
DCLKand FCLK ,So by using 8 chips of AFE5809 ,my design come out total 8 clocks of DCLK and 8 clocks of FCLK and i need
SUGGESTION TO IMPLEMENT THESE TOTAL 16 CLOCKS TO INTERFACE TO FPGA EITHER USE MUX/BUFFER
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Unexpected fread() behavior
I'm using fopen(, "rb") and fread() as part of a test bench (simulator) for a small block a code. Because I am single stepping through the code and usually aborting execution to reload a code change, the fclose() never gets called. Can repeated calls to fopen() with the same file name cause a problem (using up all the file handles, or not resetting file pointers)?
What I'm observing is that every 10-12 calls to fread(), a block of data gets skipped as if the previous fread() extracted twice the data requested. However, size= fread() so does not flag a discrepancy with the requested number of elements. Since I'm trying to read in MPEG-2 TS packets, I'm observing that the continuity count skips while scrutiny of the source file shows all the data is in fact present.
Another thought, even though this is a simulator (not emulator) do you need to call cache_inv() to sync up the data just read?
-Calvin
CCS 5.5.0.00077
CGT 6.1.20
Target: C6472 (Simulator)
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Help ADS1248 IDAC problem: no current
As the schematic below:
External Reference：REF0，2V
PGA：16
IDAC：500uA
RTD: PT100
Capacitors C6-C17 are not soldered yet
150 Ohm resistors take the RTDs’ places in the test
ADS1248 register setting:：
00 1H
01 0H
02 20H
03 42H
04 0H
05 0H
06 0H
07 40H
08 15H
09 40H
0A 84H
0B 1H
0C 0H
0D 0H
0E 0H
Test Result:
RTD1-1 and AIN0 connected, RTD1-2，RTD1-3, AIN1，BIAS connected，the end of R1 which should be connected to GND is tested.
DVDD4.63V，AVDD3.16V，
No current on RTD1-1, RTD1-2 or RTD1-3
Voltage between R1: 0
Question 1:
Why no IDAC current?
Question 2:
If IDAC current worked correctly, with pt100 and temperature range is 0-400 degree C (100-247.98ohm), Could it be compliant with analog voltage restriction for ADS1248?
Question 3：
Does the capacitor filter real reduce errors? Are the values OK? Is there any suggestion?
Question 4：
If RC filter are used, does ADS1248 have to have 2 ports to provide IDAC and only up to 2 pt100s can be measured?
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Inorder to provide the galvanic isolation for circuit
Sir,
I have found LMR 24210 regulator having input 28V and outputs are 3.3V-0.8A, 15V-0.1A, 5V-0.4A can we provide galvanic isolation of the output voltages between each other and from primary circuit
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LM25085 not bucking
We are testing a circuit designed with webench using the LM25085A. Vin 13.5-16V, Vout 12V, 5A. The circuit will pass through V when it is turned on but does not appear to be regulating. For example if we supply 14, 15 , or 16 V the output is the same as the input . Appreciate any suggestions. Thanks
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REF5020 noise spec
Hi,
We are planning to use REF5020 as a reference input to characterize CT front end device for which integrated noise is a very critical spec. So we want to know REF5020 integrated noise till say 10M. I simulated REF5020 model using TINA and found it reaches to 33uV as shown in below plot which seems to be quite high. So I was wondering whether noise has been modeled correctly or not. So could any one have idea about integrated noise of REF5020 till 10MHz?
Thanks
Regards,
Shabbir
Design engineer
Texas instruments, India
+91-9243532152
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