Part Number:TXB0304
Hi Team,
My customer wants to use TXB0304 to transfer a 19.2MHz clock(0.8Vpp ) from TCXO to a 1.8Vpp clock,but there are some jitter requirement for 1.8Vpp clock.
Do we have data about how much additional jitters will add to TXB0304B output when it used as a clock buffer?
And do we have any suggestion for the application that use level shift as clock buffer with low additional jitter?
Best Regards,
Nick Dai
Part Number:TLV320AIC3254
Hi,
Trying to understand the difference between CM1 and CM2 (the DS and the AN do not contain many information about it), I found this post which makes sense.
In this regard it is not clear to me the difference between these two situations:
A) {Register, Value}
{0x00,0x01} //page 1
{0x34,0x40}, // leftP ->IN1L
{0x36,0x01}, // leftN ->CM2L
{0x37,0x00}, //rightP OFF
{0x39,0x00}, //rightN OFF
{0x3b,0x1d}, //left micpga
{0x3c,0x1d}, //right micpga
{0x33,0x68}, //mic biasand B)
same as A) but
{0x36,0x40}, //leftN ->CM1LWith A) using CM2L I can hear the signal, with B) i.e. CM1L I can't.
Thank you.
Part Number:CC3220
I've recently began a project working with the CC3220S and CC3220SF variants and had a couple of questions regarding porting the CC3200 OTA to the CC3220.
It looks as if the sl_extlib functionality that was used for the CC3200 OTA has been folded into the CC3220 sl_fsCtl. The example projects in the simplelink sdk all show the example of updating the CC3220 via an archive. Is there any examples showing only updating the firmware file?
Due to some sizing constraints I may be needing to utilize the SF model and I was wondering if you have the ability to not utilize code signing for my firmware file?
Lastly, if I have to do code signing what does the CC3220 do when the code signing certificate expires? What happens when the factory image has an expired code signing certificate?
Thanks.
Part Number:TLV2404
Part Number:TMS320C6678
Tool/software:TI-RTOS
Hi
I spent a lot of time for integrating NDK and SRIO but I couldn't integrate the modules finally. I am so sad, Please help me to solve the problem.
My tools:
OS: win7
CCS: 7
The sequense of calling my functions(in the main()) are as below:
1) Qmss_Cppi_PA_Init();
2) SRIO (enable_srio();, SrioDevice_init();, Srio_init(); and clearSrioStatusErrors(); )
3) GPIO_INIT();
4) setupSRIOAppConfig((Qmss_MemRegion)Qmss_MemRegion_MEMORY_REGION1); .
In stage one I declared and init Qmss, Cppi, and PA as below:
void Qmss_Cppi_PA_Init(){
Qmss_MemRegInfo memRegInfo;
int32_t result;
int i,coreNum;
QMSS_CFG_T qmss_cfg;
CPPI_CFG_T cppi_cfg;
/* Get information about the platform so we can use it in various places */
memset( (void *) &gPlatformInfo, 0, sizeof(platform_info));
(void) platform_get_info(&gPlatformInfo);
(void) platform_uart_init();
(void) platform_uart_set_baudrate(115200);
(void) platform_write_configure(PLATFORM_WRITE_ALL);
/* Clear the state of the User LEDs to OFF */
for (i=0; i < gPlatformInfo.led[PLATFORM_USER_LED_CLASS].count; i++) {
(void) platform_led(i, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
}
coreNum =CSL_chipReadReg (CSL_CHIP_DNUM);
/* Initialize the components required to run this application:
* (1) QMSS
* (2) CPPI
* (3) Packet Accelerator
*/
/* Initialize QMSS */
if (coreNum == 0)
{
qmss_cfg.master_core = 1;
}
else
{
qmss_cfg.master_core = 0;
}
qmss_cfg.max_num_desc = MAX_NUM_DESC+ NUM_HOST_DESC; //256
qmss_cfg.desc_size = MAX_DESC_SIZE; //128
qmss_cfg.mem_region = Qmss_MemRegion_MEMORY_REGION0;
if (res_mgr_init_qmss (&qmss_cfg) != 0)
{
System_printf ("Failed to initialize the QMSS subsystem \n");
}
else
{
System_printf ("QMSS successfully initialized \n");
}
/* Initialize CPPI */
if (coreNum == 0)
{
cppi_cfg.master_core = 1;
}
else
{
cppi_cfg.master_core = 0;
}
cppi_cfg.dma_num = Cppi_CpDma_PASS_CPDMA;
cppi_cfg.num_tx_queues = NUM_PA_TX_QUEUES;
cppi_cfg.num_rx_channels = NUM_PA_RX_CHANNELS;
if (res_mgr_init_cppi (&cppi_cfg) != 0)
{
System_printf ("Failed to initialize CPPI subsystem \n");
}
else
{
System_printf ("CPPI successfully initialized \n");
}
if (res_mgr_init_pass()!= 0) {
System_printf ("Failed to initialize the Packet Accelerator \n");
}
else
{
System_printf ("PA successfully initialized \n");
}
}
I only modyfied " res_mgr_init_qmss() " fanction as below and other functions were without any changes:
int32_t
res_mgr_init_qmss
(
QMSS_CFG_T *p_qmss_cfg
)
{
Qmss_MemRegInfo memRegInfo; //M.A
int32_t result;
Qmss_MemRegInfo memCfg;
Qmss_InitCfg qmssInitConfig;
Cppi_DescCfg cppiDescCfg;
uint32_t numAllocated;
if (p_qmss_cfg->master_core)
{
/* Initialize QMSS */
memset (&qmssInitConfig, 0, sizeof (Qmss_InitCfg));
/* Set up QMSS configuration */
/* Use internal linking RAM */
qmssInitConfig.linkingRAM0Base = 0;
qmssInitConfig.linkingRAM0Size = 0;
qmssInitConfig.linkingRAM1Base = 0x0;
qmssInitConfig.maxDescNum = p_qmss_cfg->max_num_desc;
qmssInitConfig.pdspFirmware[0].pdspId = Qmss_PdspId_PDSP1;
#ifdef _LITTLE_ENDIAN
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_le;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_le);
#else
qmssInitConfig.pdspFirmware[0].firmware = (void *) &acc48_be;
qmssInitConfig.pdspFirmware[0].size = sizeof (acc48_be);
#endif
/* Initialize the Queue Manager */
#if defined(DEVICE_K2H) || defined(DEVICE_K2K)
result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams);
#else
result = Qmss_init (&qmssInitConfig, &qmssGblCfgParams[0]);
#endif
if (result != QMSS_SOK)
{
platform_write ("Error initializing Queue Manager SubSystem, Error code : %d\n", result);
return -1;
}
}
/* Start Queue manager on this core */
Qmss_start ();
/* Setup the descriptor memory regions.
*
* The Descriptor base addresses MUST be global addresses and
* all memory regions MUST be setup in ascending order of the
* descriptor base addresses.
*/
/* Initialize and setup CPSW Host Descriptors required for example */
memset (Ethernet_region, 0, /*128*128*/MAX_DESC_SIZE_ETH * NUM_DESC_ETH);
memCfg.descBase = (uint32_t *) Convert_CoreLocal2GlobalAddr ((uint32_t) Ethernet_region);
memCfg.descSize = MAX_DESC_SIZE_ETH;//128;//64;//
memCfg.descNum = NUM_DESC_ETH;//128;//
memCfg.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
memCfg.memRegion = p_qmss_cfg->mem_region;
memCfg.startIndex = 0;
/* Insert Host Descriptor memory region */
result = Qmss_insertMemoryRegion(&memCfg);
if (result == QMSS_MEMREGION_ALREADY_INITIALIZED)
{
platform_write ("Memory Region %d already Initialized \n", memCfg.memRegion);
}
else if (result < QMSS_SOK)
{
platform_write ("Error: Inserting memory region %d, Error code : %d\n", memCfg.memRegion, result);
return -1;
}
/* Initialize all the descriptors we just allocated on the
* memory region above. Setup the descriptors with some well
* known values before we use them for data transfers.
*/
memset (&cppiDescCfg, 0, sizeof (cppiDescCfg));
cppiDescCfg.memRegion = p_qmss_cfg->mem_region;
cppiDescCfg.descNum = NUM_DESC_ETH;//128;//
cppiDescCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;
cppiDescCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
cppiDescCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;
cppiDescCfg.descType = Cppi_DescType_HOST;
/* By default:
* (1) Return descriptors to tail of queue
* (2) Always return entire packet to this free queue
* (3) Set that PS Data is always present in start of SOP buffer
* (4) Configure free q num < 4K, hence qMgr = 0
* (5) Recycle back to the same Free queue by default.
*/
cppiDescCfg.returnPushPolicy = Qmss_Location_TAIL;
cppiDescCfg.cfg.host.returnPolicy = Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;
cppiDescCfg.cfg.host.psLocation = Cppi_PSLoc_PS_IN_DESC;
cppiDescCfg.returnQueue.qMgr = 0;
cppiDescCfg.returnQueue.qNum = QMSS_PARAM_NOT_SPECIFIED;
cppiDescCfg.epibPresent = Cppi_EPIB_EPIB_PRESENT;
/* Initialize the descriptors, create a free queue and push descriptors to a global free queue */
if ((gGlobalFreeQHnd = Cppi_initDescriptor (&cppiDescCfg, &numAllocated)) <= 0)
{
platform_write ("Error Initializing Free Descriptors, Error: %d \n", gGlobalFreeQHnd);
return -1;
}
if (numAllocated != cppiDescCfg.descNum) {
platform_write ("function Init_Qmss: expected %d descriptors to be initialized, only %d are initialized\n", cppiDescCfg.descNum, numAllocated);
//return (-1);
}
/* Initialize the Host Region. */
memset ((void *)&SRIO_region, 0, sizeof(SRIO_region));
/* Memory Region Configuration */
memRegInfo.descBase = (uint32_t *)Convert_CoreLocal2GlobalAddr((uint32_t)SRIO_region);
memRegInfo.descSize = MAX_DESC_SIZE_SRIO;/*p_qmss_cfg->desc_size*/;//SIZE_HOST_DESC;
memRegInfo.descNum = NUM_DESC_SRIO;//p_qmss_cfg->max_num_desc;//NUM_HOST_DESC;
memRegInfo.manageDescFlag = Qmss_ManageDesc_MANAGE_DESCRIPTOR;
memRegInfo.memRegion = Qmss_MemRegion_MEMORY_REGION1;
memRegInfo.startIndex = 128;//0;//
/* Initialize and inset the memory region. */
result = Qmss_insertMemoryRegion (&memRegInfo);
if (result < QMSS_SOK)
{
platform_write ("Error inserting memory region: %d\n", result);
return;
}
/* Queue Manager Initialization Done */
return 0;
}
In stage two I only modify " SrioDevice_init() " function that I can communicate to FPGA.
In stage three I init GPIO that I think it didn't have the effect on the problem.
In stage four I called " setupSRIOAppConfig() ". I called this function with a separate memory region " Qmss_MemRegion_MEMORY_REGION1" from Ethernet memory region "Qmss_MemRegion_MEMORY_REGION0".
static int32_t setupSRIOAppConfig (Qmss_MemRegion memRegion)
{
Qmss_QueueHnd myRxFreeQueueHnd;
Qmss_QueueHnd myRxCompletionQueueHnd;
Qmss_QueueHnd tmpQueueHnd;
UInt32 numAllocated;
int32_t eventId;
UInt8 isAllocated;
Cppi_DescCfg descCfg;
UInt16 index;
Cppi_HostDesc* ptrHostDesc;
UInt8* ptrRxData;
UInt32 numRxBuffers;
Srio_DrvConfig drvCfg;
Srio_DrvHandle drvHandle;
CSL_SrioHandle hSrioCSL;
// char buffer[MAX_MESSAGE_SIZE];
Error_Block errorBlock; //M.A
/* Initialize the SRIO Driver Configuration. */
memset ((Void *)&drvCfg, 0, sizeof(Srio_DrvConfig));
/* Initialize the OSAL
* Gets 30 buffers of mtu size. 30 is hard coded in the OSAL.
* */
if (Osal_dataBufferInitMemory(SRIO_MAX_MTU) < 0)
{
return NULL;
}
/********************************************************************************
* The SRIO Driver Instance is going to be created with the following properties:
* - Application Managed
* - Receive Completion Queue is Application specified; which implies that there
* is no interrupt support. Applications will hence need to poll the queue to
* check if there is data available or not.
* - The Receive Free Descriptor Queues along with the Size thresholds are
* managed and created by the application.
********************************************************************************/
/* Create the application receive free queue. */
myRxFreeQueueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED,&isAllocated);
if (myRxFreeQueueHnd < 0)
{
return NULL;
}
/* Create the application receive completion queue. */
myRxCompletionQueueHnd = Qmss_queueOpen (Qmss_QueueType_GENERAL_PURPOSE_QUEUE, QMSS_PARAM_NOT_SPECIFIED,&isAllocated);
if (myRxCompletionQueueHnd < 0)
{
return NULL;
}
/* We are going to be using 4 receive buffers in this example. */
numRxBuffers = 4;
/* Application created queue which stores all the receive buffers. */ //M.A
descCfg.memRegion = Qmss_MemRegion_MEMORY_REGION1;//Qmss_MemRegion_MEMORY_REGION0; // aligns to Host region that was set in init, it was not specified which means it will be zero.
descCfg.descNum = numRxBuffers;
descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;
descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;
descCfg.descType = Cppi_DescType_HOST;
descCfg.returnQueue = Qmss_getQueueNumber(myRxFreeQueueHnd);
descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;
descCfg.returnPushPolicy = Qmss_Location_HEAD;
descCfg.cfg.host.returnPolicy = Cppi_ReturnPolicy_RETURN_ENTIRE_PACKET;
descCfg.cfg.host.psLocation = Cppi_PSLoc_PS_IN_DESC;
tmpQueueHnd = Cppi_initDescriptor (&descCfg, &numAllocated);
if (tmpQueueHnd < 0 || numAllocated < 1)
{
return NULL;
}
/* Initialize the application receive buffers. */
for (index = 0; index < descCfg.descNum; index++)
{
/* Pop off a descriptor */
ptrHostDesc = (Cppi_HostDesc *)Qmss_queuePop(tmpQueueHnd);
if (ptrHostDesc == NULL)
{
return NULL;
}
/* Allocate the receive buffer where the data will be received into by the SRIO CPDMA. */
/* Make sure to adjust the RX buffer size to work around the SRIO CPDMA issue. */
ptrRxData = (uint8_t*)Memory_alloc (NULL, (MESSAGE_MAX_DATA_SIZE+RX_BUFFER_BYTES_ADJUSTMENT), 0, &errorBlock);
if (ptrRxData == NULL)
return -1;
/* Convert the address to a global address. */
ptrRxData = (uint8_t*)l2_global_address((uint32_t)ptrRxData);
/* Allocate the receive buffer where the data will be received into by the SRIO CPDMA.
* osal_srio grabs one of the 30 buffers allocated by the init function. */
// ptrRxData = (UInt8*)Osal_srioDataBufferMalloc(SRIO_MAX_MTU);
// if (ptrRxData == NULL)
// {
// return NULL;
// }
/* Set the DATA and ORIGNAL DATA in the buffer descriptor. */
Cppi_setData (Cppi_DescType_HOST, (Cppi_Desc*)ptrHostDesc, (UInt8*)ptrRxData, SRIO_MAX_MTU);
Cppi_setOriginalBufInfo (Cppi_DescType_HOST, (Cppi_Desc*)ptrHostDesc, (UInt8*)ptrRxData, SRIO_MAX_MTU);
/* Add the packet descriptor to the Application Receive Free Queue. */
Qmss_queuePushDescSize (myRxFreeQueueHnd, (UInt32*)ptrHostDesc, SIZE_HOST_DESC);
}
/* Close the temporary queue. */
Qmss_queueClose (tmpQueueHnd);
/********************************************************************************
* The SRIO Driver Instance is going to be created with the following properties:
* - Driver Managed
* - Interrupt Support (Pass the Rx Completion Queue as NULL)
********************************************************************************/
/* Setup the SRIO Driver Managed Configuration. */
drvCfg.bAppManagedConfig = FALSE;
/* Driver Managed: Receive Configuration */
drvCfg.u.drvManagedCfg.bIsRxCfgValid = 1;
drvCfg.u.drvManagedCfg.rxCfg.rxMemRegion = Qmss_MemRegion_MEMORY_REGION1; //Qmss_MemRegion_MEMORY_REGION0; //M.A
drvCfg.u.drvManagedCfg.rxCfg.numRxBuffers = 4;
drvCfg.u.drvManagedCfg.rxCfg.rxMTU = SRIO_MAX_MTU;
/* Accumulator Configuration. */
int32_t coreToQueueSelector[4];
/* This is the table which maps the core to a specific receive queue. */
//These were chosen based on using event 49 instead of 48. NDK uses 48
coreToQueueSelector[0] = 712;
coreToQueueSelector[1] = 713;
coreToQueueSelector[2] = 714;
coreToQueueSelector[3] = 715;
/* Since we are programming the accumulator we want this queue to be a HIGH PRIORITY Queue */
drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue = Qmss_queueOpen (Qmss_QueueType_HIGH_PRIORITY_QUEUE,coreToQueueSelector[0/*CORE_NUM*/], &isAllocated);
if (drvCfg.u.drvManagedCfg.rxCfg.rxCompletionQueue < 0)
{
return NULL;
}
/* Accumulator Configuration is VALID. */
drvCfg.u.drvManagedCfg.rxCfg.bIsAccumlatorCfgValid = 1;
/* Accumulator Configuration. */
drvCfg.u.drvManagedCfg.rxCfg.accCfg.channel = NUM_PA_TX_QUEUES+NUM_PA_RX_CHANNELS;//+CORE_NUM; //M.A
drvCfg.u.drvManagedCfg.rxCfg.accCfg.command = Qmss_AccCmd_ENABLE_CHANNEL;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.queueEnMask = 0;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.queMgrIndex = coreToQueueSelector[0/*CORE_NUM*/];
drvCfg.u.drvManagedCfg.rxCfg.accCfg.maxPageEntries = 2;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.timerLoadCount = 0;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.interruptPacingMode = Qmss_AccPacingMode_LAST_INTERRUPT;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.listEntrySize = Qmss_AccEntrySize_REG_D;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.listCountMode = Qmss_AccCountMode_ENTRY_COUNT;
drvCfg.u.drvManagedCfg.rxCfg.accCfg.multiQueueMode = Qmss_AccQueueMode_SINGLE_QUEUE;
/* Initialize the accumulator list memory */
memset ((Void *)&gHiPriAccumList1[0], 0, sizeof(gHiPriAccumList1));
drvCfg.u.drvManagedCfg.rxCfg.accCfg.listAddress = l2_global_address((UInt32)&gHiPriAccumList1[0]);
/* Driver Managed: Transmit Configuration */
drvCfg.u.drvManagedCfg.bIsTxCfgValid = 1;
drvCfg.u.drvManagedCfg.txCfg.txMemRegion = Qmss_MemRegion_MEMORY_REGION1;//Qmss_MemRegion_MEMORY_REGION0; //M.A
drvCfg.u.drvManagedCfg.txCfg.numTxBuffers = 4;
drvCfg.u.drvManagedCfg.txCfg.txMTU = SRIO_MAX_MTU;
/* Start the Driver Managed SRIO Driver. Calls Cppi_open for SRIO */
hAppManagedSrioDrv = Srio_start(&drvCfg);
if (hAppManagedSrioDrv == NULL)
{
return NULL;
}
//Hook up the SRIO interrupt with the core. Don't use standard 48 becuase ndk is using that.
EventCombiner_dispatchPlug (49, (EventCombiner_FuncPtr)Srio_rxCompletionIsr, (UArg)hAppManagedSrioDrv, TRUE);
EventCombiner_enableEvent(49);
/* Get the CSL SRIO Handle. */
hSrioCSL = CSL_SRIO_Open (0);
/* SRIO DIO Interrupts need to be routed from the CPINTC0 to GEM Event.
* - We have configured DIO Interrupts to get routed to Interrupt Destination 0
* (Refer to the CSL_SRIO_RouteLSUInterrupts API configuration in the SRIO Initialization)
* - We want this System Interrupt to mapped to Host Interrupt 8 */
/* Disable Interrupt Pacing for INTDST0 */
CSL_SRIO_DisableInterruptPacing (hSrioCSL, 0);
/* Route LSU0 ICR0 to INTDST0 */
CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 0, 0);
/* Route LSU0 ICR1 to INTDST0 */
CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 1, 0);
/* Route LSU0 ICR2 to INTDST0 */
CSL_SRIO_RouteLSUInterrupts (hSrioCSL, 2, 0);
/* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
CpIntc_dispatchPlug(CSL_INTC0_INTDST0, (CpIntc_FuncPtr)myDIOIsr, (UArg)hAppManagedSrioDrv, TRUE);
/* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
CpIntc_mapSysIntToHostInt(0, CSL_INTC0_INTDST0, 8);
/* Enable the Host Interrupt. */
CpIntc_enableHostInt(0, 8);
/* Enable the System Interrupt */
CpIntc_enableSysInt(0, CSL_INTC0_INTDST0);
/* Get the event id associated with the host interrupt. */
eventId = CpIntc_getEventId(8);
/* Plug the CPINTC Dispatcher. */
EventCombiner_dispatchPlug (eventId, (EventCombiner_FuncPtr)CpIntc_dispatch, 8, TRUE);
return (int32_t)hAppManagedSrioDrv;
}
I should mentioned that I called SRIO and DIO in two tasks.
Best Regards
Part Number:DS90UB954-Q1
Hello,TI experts，
I have below questions really need your help:
1. I want use two DS90UB933,compliant with a DS90UB954,How to set the DS90UB954 data 4 lanes configuration to know data comes from which DS90UB933?How to organize the data?
2.When DS90UB954 coupled with DS90UB933,What's the delay range between 954 GPIO and 933's ends？What's the max/typ/min delay time?
Looking fowards to your kindly respond,thank you very much~
Part Number:CC3200MOD
Hi everyone,
Kindly help me to review this charging circuit.
Charging Circuit: Charging for LI-PO 4.2V
Switching regulator: Switch 4.2 (output of charging circuit) to 3.3V (apply for my CC3200MOD system).
If I have bothplugin USB and using BAT for the system. What's happen?
Thank you so much!
Thanks & Best Regards,
NhatThanh
Part Number:PROCESSOR-SDK-AM335X
Tool/software: Linux
Hi Team
Kindly please help with testing i2c with the eeprom present on beagle bone board
I am posted more than 3 times but got no proper procedure /response on testing on this
I kindly request you to help
Need to test i2c driver using i2c tools BOTH read and write
I always get error on write or read failed
Please check and help me There are many posts that I have done you can have a look
Thank you
Deepak R
Part Number:CC2538-CC2592EMK
Tool/software: Linux
I followed this issue (github.com/.../1023) and accordingly changed my portion of the code in cc2538-rf.c :
#define EN_LNA_PIN (1 << 2) #define PAEN_PIN (1 << 3) #define HGM_PIN (1 << 2) GPIO_SET_OUTPUT(GPIO_C_BASE, PAEN_PIN); GPIO_WRITE_PIN(GPIO_C_BASE, PAEN_PIN, 1); GPIO_SET_OUTPUT(GPIO_C_BASE, EN_LNA_PIN); GPIO_WRITE_PIN(GPIO_C_BASE, EN_LNA_PIN, 1); // PD0 -> 0/1 -> High/Low Gain GPIO_SET_OUTPUT(GPIO_D_BASE, HGM_PIN); GPIO_WRITE_PIN(GPIO_D_BASE, HGM_PIN, 0); REG(RFCORE_XREG_RFC_OBS_CTRL0) = 0x6A; REG(RFCORE_XREG_RFC_OBS_CTRL1) = 0x68; REG(CCTEST_OBSSEL2) = 0x80; REG(CCTEST_OBSSEL3) = 0x81;
I am unable to get the simple-udp-rpl broadcast example, still doesn't send anything. Am I missing anything here?
Part Number:TAS5733L
Hi,
The TAS5733L is being considered in for a new design. The part drives up to 2 speakers at 10W. However, the design only has a single 10W speaker. The design uses an I2S audio output, so this is a requirement. This part seems to be cost competitive, even if it is over specified. Can you please review the design and suggest if there is any saving to be made on external components?
Many thanks,
Ross
Part Number:TLV320ADC3101
Is it possible to control the slew rate on the WCLK, BCLK, DOUT signals via software/I2C control on this part?
Or maybe control the output current? Anything that would help with emissions (EMC) performance?
I searched the datasheet for the word "slew" and didn't find it.
I briefly reviewed all registers and didn't find anything.
Just checking here in case I missed something.
Part Number:TMDSLCDK138
Tool/software: Code Composer Studio
Hello,
During installation of CCSv7.3 installation stops due to an error. Attached are installation log file
(Please visit the site to view this file)
Thanks,
Itzhak Kroin
Part Number:TLV320AIC3104
Tool/software: Code Composer Studio
Hi all,
the communication between the microcontroller and the audio-codec ist not working. It get stucked in the function "WriteReg_AIC" in the 5th line. I want to configure the audio-codec as ADC and DAC but I cant´t get any communication to it. Can anybody help me?
void Init_I2C (void)
{
//SysCtlPeripheralReset(SYSCTL_PERIPH_I2C1);
SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C1); // enable I2C
//SysCtlPeripheralReset(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); // enable GPIOA
while(!SysCtlPeripheralReady(SYSCTL_PERIPH_I2C1) && !SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOA)); // wait until modules are ready
GPIOPinTypeI2CSCL(GPIO_PORTA_BASE, GPIO_PIN_6); // configure pin for use as I2CSCL
GPIOPinTypeI2C(GPIO_PORTA_BASE, GPIO_PIN_7); // configure pin for use as I2CSDA
GPIOPinConfigure(GPIO_PA6_I2C1SCL); // configure pin muxing
GPIOPinConfigure(GPIO_PA7_I2C1SDA);
I2CMasterInitExpClk(I2C1_BASE, SysCtlClockGet(), false); // initalize I2C Master (100 Kbps)
}
_Bool WriteReg_AIC(uint32_t ucReg, uint32_t ucBits)
{
I2CMasterSlaveAddrSet(I2C1_BASE, SLAVE_ADDR_AIC3104, false);
I2CMasterDataPut(I2C1_BASE, ucReg);
while(I2CMasterBusBusy(I2C1_BASE));
I2CMasterControl(I2C1_BASE, I2C_MASTER_CMD_BURST_SEND_START);
while(I2CMasterBusy(I2C1_BASE));
if(I2CMasterErr(I2C1_BASE) != I2C_MASTER_ERR_NONE) return false;
I2CMasterDataPut(I2C1_BASE, ucBits);
I2CMasterControl(I2C1_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);
while(I2CMasterBusy(I2C1_BASE));
if(I2CMasterErr(I2C1_BASE) != I2C_MASTER_ERR_NONE) return false;
return true;
}
void Init_ADC(void)
{
WriteReg_AIC(19, 0x07); // LINE1LP to Left-ADC, single-ended, gain=0dB, power up, soft-stepping=off
WriteReg_AIC(22, 0x07); // LINE1RP to Right-ADC, single-ended, gain=0dB, power up, soft-stepping=off
WriteReg_AIC(15, 0x80); // left-ADC PGA is not muted, gain=0dB
WriteReg_AIC(16, 0x80); // right-ADC PGA is not muted, gain=0dB
}
void Init_DAC(void)
{
WriteReg_AIC(7, 0x0A); // left DAC to left channel and right DAC to right channel, fs(ref)=48kHz
WriteReg_AIC(37, 0xE0); // power up left and right DAC, HPLCOM is single ended
WriteReg_AIC(41, 0x00); // DAC_L1 and DAC_R1 for routing to Line out and HP OUT, left and right DAC have independent volume control
WriteReg_AIC(43, 0x00); // left volume, mute=off, gain=0db
WriteReg_AIC(44, 0x00); // right volume, mute=off, gain=0db
WriteReg_AIC(47, 0x80); // DAC_L1 to HPLOUT (headphone)
WriteReg_AIC(51, 0x0F); // power up HPLOUT
WriteReg_AIC(64, 0x80); // DAC_R1 to HPROUT (headphone)
WriteReg_AIC(65, 0x0F); // power up HPROUT
WriteReg_AIC(82, 0x80); // DAC_L1 to LEFT_LOP/M (line out)
WriteReg_AIC(86, 0x09); // power up LEFT_LOP/M
WriteReg_AIC(92, 0x80); // DAC_R1 to RIGHT_LOP/M (line out)
WriteReg_AIC(93, 0x09); // power up RIGHT_LOP/M
}
void Init_AIC3104(void)
{
Init_I2C();
WriteReg_AIC(0, 0x00); // page select
WriteReg_AIC(1, 0x80); // software reset
WriteReg_AIC(8, 0xC0); // BCLK and WCLK as output (master mode)
WriteReg_AIC(9, 0x00); // I2S mode, 16 bits (word length)
WriteReg_AIC(10, 0x00); // no data offset
Init_ADC();
Init_DAC();
}
Part Number:ADS1256
I am using a Waveshare ADS1256 board to read gas sensor connected through LMP91000. I am using VRef 2.048 on the LMP91000. I have tried connecting the Vref from LMP91000 to the Vref on the ADS1256 board with the AINCOM tied to ground. I have also tried using the ADS1256 builtin 2.5V Vref. In both case the Vref 2.048 from LMP91000 is also connected to A0 on ADS1256. However the Voltage sensed on A0 is 2.069. Can you please let me know what I should do to get the correct ref voltage of 2.048V. The PGA is set to 1, ACAL to 1. I am a newbie so please try to explain elaborately.
Regards
Vijay
Part Number:MSP430FR4133
Tool/software: Code Composer Studio
Hi TI-Forum, I can't build this code. How can I fix the error "unsolved symbolds"?
#include <msp430fr4133.h>
#include <driverlib.h>
#include "main.h"
#include "hal_LCD.h"
#include <stdio.h>
#include <stdlib.h>
int main(void) {
// Stop Watchdog timer
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
Init_LCD();
displayScrollText("WELCOME TO THE FR4133 LAUNCHPAD");
}Errors:
Description Resource Path Location Type
#10010 errors encountered during linking; "LCD mit Test_2.out" not built LCD mit Test_2 C/C++ Problem
<a href="file:/c:/ti/ccsv6/tools/compiler/dmed/HTML/10234.html">#10234-D</a> unresolved symbols remain LCD mit Test_2 C/C++ Problem
unresolved symbol mode, first referenced in<whole-program> LCD mit Test_2 C/C++ Problem
Part Number:TS3DV20812
Hi Team,
My customer is just looking for bi-directional differential switch for MADI communication, 125MHz. They would like to switch input lines and output lines by controlling GPIO level provided from MCU.
Here is their requirement for the SW
- Number of channel : more than 3ch
- BW : be able to pass MADI signal(125MHz), so should be more than 625MHz(5th harmonic)?
- Supply voltage : 2.5 V support is preferred(But other levels might also acceptable)
- Input-Output Type : CML is better but other standards also OK such as LVDS.
I think TS3DV20812 meets their requirement but could you review if it works properly or not?
If you have another solution, any suggestion will be appreciated.
Regards,
Takashi Onawa
Part Number:INA213
Hello
Please, tell me any one, how to correctly calculate the shunt for INA213?
I need to measure a direct current up to 10A & 0..24V (Laboratory Power Supply)
In my MCU vref = 3.3V and ADC max range some 3.3V
V+ need 3.3? or V+ in the INA213 must be connected to power line..? V+ maybe less Vin?
i read datasheet and have doubts
PS.
I made the right choice by buying ina213?
thank you
Part Number:MSP430FR4133
Hi everyone,
I am trying to learn how to use timers on the MSP-EXP430FR4133 development board but I am having difficulty understanding the nomenclature of the timers and their interrupts.
From the product specific data sheet, I see that this particular chip has "Two 16-Bit Timers With Three Capture/Compare Registers Each (Timer_A3)" so I have taken this to mean that the name "Timer_A3" is the name that TI have given to the particular variant of Timer_A that happens to have 3 capture/compare registers. So far, fairly straightforward...
Now I refer to the "MSP430FR4xx and MSP430FR2xx Family User Guide" which states that "There may be multiple instantiations of Timer_A on a given device. The prefix TAx is used, where x is a greater than equal to zero indicating the Timer_A instantiation. For devices with one instantiation, x = 0. The suffix n, where n = 0 to 6, represents the specific capture/compare registers associated with the Timer_A instantiation."
So, this would lead me to believe that my two timers are called TA0 and TA1. Is this correct?
Where I get confused is when I try to understand the naming of the interrupt vectors... I have been given the following example code which runs as intended on the device.
#include <msp430.h>
#include <driverlib.h>
volatile bool TimerA0_CCR0_interrupt_hit = 0;
volatile unsigned int TimerA0_period = 16000;
#pragma vector = TIMER0_A0_VECTOR //Timer A0 interrupt ISR
__interrupt void TIMERA0_ISR0(void)
{
TimerA0_CCR0_interrupt_hit=1; //On A0 interrupt hit, set the flag
}
#pragma vector = TIMER0_A1_VECTOR //Timer A1 interrupt ISR
__interrupt void TIMERA0_ISR1(void)
{
switch(__even_in_range(TA0IV,10)) //Clears the flag
{
; //Not used
}
}
So here we see Timer 0 being referred to as TIMER0_A0_VECTOR. Where has this "A" come from and why is it not "A3"?
Also, as I understand it, the TIMERA0_ISR0(void) above is triggered ONLY by a capture/compare interrupt from timer TA0. Furthermore, TIMERA0_ISR1(void), is triggered by any other interrupts originating from TA0 which in this case I am not interested in because I just use the c/c interrupt to blink an LED. Is my understanding of this correct?
Sorry for the long winded post. I think I understand the concepts but I'm really struggling with the intricacies of the interrupt vector names.
Part Number:TPS28225
Dear polite inhabitants of this forum,
this time I'd like to ask something as a hobbyist :-)
I'm considering a "project" where I would use a symmetrical source of +/- 5V (relative to GND), to be fed from a 12V upstream PSU rail. I don't need anywhere near 120 Watt, but with respect to efficiency, I'm curiously eyeing some sync-rectified designs with an isolated secondary. Call it an academic interest at this stage :-)
I have noticed an interesting schematic in an article at eetimes.com that turns out to refer to a TI reference board called the PMP4123. It has a secondary-side MOSFET driver, synchronized across the isolation gap using low-latency capacitive couplers (isolators). At a first sight, this is so neat, nifty.
There's one thing that's caught my eye: I didn't understand how the LGATE driver in the TPS28225 knows when to switch off. Superficially and intuitively I thought the rectifier would go "UGATE, LGATE, idle" at lower than 100% load - and I was investigating in vain, in the TPS28225 datasheet, how it gets to know about the final "zero crossing" (at which moment it's time to go high-Z). There is nothing to indicate that the TPS28225 finds out somehow on its own, it doesn't have a current sensing input. There does seem to be a way to tri-state this MOSFET driver, if you provide it with an input level "inside the 3-state window", which spans about 50% of the input range, centered in the middle between GND and full log.1. The response time to the 3-state window is about 250 ns = not very fast, likely impractical for cycle-by-cycle rectifier shutoff. The ISO721 couplers can tristate their output, but only in response to their primary (transmitter) losing power. As long as the ISO721's primary part is powered, it works down to DC, but only in logic levels (it's digital, not analog). Plus, the PWM signal used as input to the isolators doesn't provide a 3rd state.
Note that there are no waveforms to be found around the aforementioned eetimes article or the reference design, to support my "UGATE, LGATE, idle" sequence. To me it was a mystery.
It only dawned on me when I looked up the UCC2897 datasheet. The catch is, that the PWM controller is "resonant". Resonant SMPS designs save power (a few per cent in efficiency) by starting the "inductor charging phase" just after the last "discharge phase" has reached a zero crossing. A resonant switcher does *not* waste a part of the duty cycle on idle time. Instead, it increases the switching frequency to back off with the output current.
And what's still unclear to me: does the PMP4123 design tolerate "down to zero" load levels? Or, does it require some minimal load on the output, corresponding to some upper limit on switching frequency?
The TPS28225 seems to be almost identical to chips from several competitors - in functionality, possibly pinout, and the typical application. This class of FET drivers is typically mentioned in the context of non-isolated buck converters, often multi-phase, for CPU VRM blocks etc. And I haven't found any application where the UGATE/LGATE duty cycle would "leave some slack of idle time" - i.e. it seems as if these chips are indeed intended for resonant designs...
Any comments welcome.
If I eventually build that isolated switcher, I will probably stick to some more conventional (and less efficient) constant-frequency design with variable duty cycle. And if I try synchronous rectification, I'll probably choose some "self-driven" secondary-side chip (PWM driver) using voltage and current sensing to determine the switching moments. Or I'll just find an off-the-shelf PCB-mount module :-)