Part Number:TMS570LS1224

Hello Team,

We are currently using TMS570LS1224 in one of our product. Our product is going for SIL2 certification. 

We used Halcogen to Create low level drivers like SPI, i2C, UART, ETPWM, Flash (FEE), RTI for os timer ticks, Mibspi, HET for PWM generation,Ecap,MibSpi,internal ADC. I would like to ask the following questions:

1) Do we need to enable any safety related options in the Halcogen??

2) As the  micro TMS570LS1224 is SIL certified. Do we need not to bother on the SIL certification ??

3) are there any Functional safety related settings in the halcogen Tool??

Please Suggest/ Provide information on SIL function safety aspects.  

Part Number:TMS320F28377D

Tool/software: Code Composer Studio

Hi,

We are using TMS320f28377D controller in one of our boards. I am facing issue while burning the code in flash. It does the erasing process and loading process and the code runs fine but when i switch off the power and switch it on, the code vanishes. I checked it with the existing the led blinking code of control suite. Changed the configuration to CPU1_FLASH.  Please guide me.

I have questions about TL594.

Question 1. 

   - In Application Report　SPRA953C,  1.2 Test Card Impact(p.3), there are 1s and 2s2p about Rθja.

    Is it 1s or 2s2p about TL594 Rθja?

Qurstion 2.

  - In datasheet p.5 REFERENCE, Output-voltage change with temperature, maximum voltage is 10mV/V.

    Are the following understandings correct?

　       Reference voltage is 5V. So, the voltage  fluctuates by 50mv(=10mV/V x 5V) .

Question 3.

  - In datasheet p.5, Frequency change with temperature, maximum frequency is 50Hz/kHz.

   Are the following understandings correct?

          For example, when frequency is 100kHz, the frequency  fluctuates by 5kHz(=50Hz/kHz x 100kHz). 

Question 4. 

  - TL594C and TL594I have different  temperature ranges.

            TL594C: 0~70°C

              TL594I: -40~85°C

    Is the fluctuate amount of TL594C and TL594I the same about Output-voltage change with temperature and Frequency change?

Best regards,

Takahiro Nishizawa

Part Number:RM48L952

Hi (again),

Even though the actual abort handler is not in the scope of SafeTI (according to safety manual) SafeTI shall still provide a method for the application to ask that "was this abort caused by it".

Current solution is not acceptable where application is forced to hack an entry to SafeTI private section and "guess" what kind of errors are trickered. Yes, demo code provides an example how to check errors but it is complete mess, #if 0 type of coding, similar pattern repeated one after one when 1 simple function call could have been done to make code more readable (axidecoder checks), also comment describes different expected value for data fault address than which is actually used and so on.

So basically this kind of interface should exists and be provided by SafeTI where the mask abort checking code from demo app's exception handler should exists
boolean bMaskDataAbort( void )

In case that is impossible (for some function call related issue, though haven't encountered one) then safety manual or some other official place should provide "approved code" which user should copy & paste to it's own exception handler to mask failures caused by SafeTI actual tests.


There is also a need to ask "is this fault injection test running", interface for that should be also provided where proper checks are made to ensure that call really comes due to fault injection:
boolean bFaultInjectionActive( SL_SelfTestType eTest )

Demo application example code does not provide an example for fault injection but proper "as much limiting check as possible" would require usage of sl_priv.c (test activity check), for that reason this code should be also provided and be under SafeTI, currently I have had to make that manually using sl_priv method and dig out what SafeTI does in order to be able to also check that FDIAGCTRL is in proper value. In case FDIAGCTRL is not in proper setting then this is real actual fault which just occured between test activity  flag set and actual fault injection
if( (SL_FLAG_GET((int32)FLASH_ADDRESS_PARITY_FAULT_INJECT)) && ((sl_flashWREG->FDIAGCTRL & 0x7U) == 7U) )
{
     ... do some own application specific fault injection magic (for example call esm callback handler and check that it has noticed this fault injection)
}

I doubt that this is as it is even "as proper" as it could be, most likely also "F021F_FDCTRL_DMODE_TEST_MODE"-bit should be checked from that register and most likely also FPAROVR register content, still it is better in current form that what was used in Demo app there was every possible test mode accepted (!= 0)... As SafeTI has the best understanding&knowing of the register settings how/when the fault is generated it shouldn't be the integrator's job to seek what SafeTI actually do in order to be able to catch/filter the proper situation...

Basically the content of the fault injection query should be something like this, to be effective there should be a separate function per fault injection test to avoid first level "if this brach, else if some other tests" seeking)...

boolean bFaultInjectionActive( SL_SelfTestType eTest )
{
     boolean bReturn = FALSE;

     if( eTest == FLASH_ADDRESS_PARITY_FAULT_INJECT )
    {
        if( SL_FLAG_GET(eTest= == TRUE )
        {
            if( some register are exactly in this and that value where SafeTI has put them )
            {
                bReturn = TRUE;
            }
   }
   return bReturn;
}



Here is example of misleading commenting (which was referenced above) in Demo application 0xFFF81000 vs actually used 0xFFFF0900 and now I should put this kind of code to my application (I have tested this test and that 0xFFFF0900 is correct one so this is just commenting error but still)...
    /*
     * DAbort due to access to illegal transcation to Peripheral Seg1 Interconnect
     * 0x00000008 indicates that it is an external abort caused by read and is AXI decode error
     * 0xFFF81000 is the reserved location accessed to create the Peripheral Seg1 interconnect error trap AXI decode error
     */
    if ((TRUE == SL_FLAG_GET(PERIPHSEGINTRCNT_RESERVED_ACCESS)) &&
        ((0x00000008u == (0x00000008u & _SL_Get_DataFault_Status())) &&
        (0xFFFF0900 == _SL_Get_DataFault_Address()))) {
        maskDAbort = TRUE;
    }

And just by a bit or work this could be written into much more readable form reducing 2 code lines per if and making impossible to make some kind of type != vs == mistake into one of the multiple similar checks
    if( bDataAbortAxiDecoder( (int32)PERIPHSEGINTRCNT_RESERVED_ACCESS, 0x00000008u, 0xFFFF0900U ) ) // NOTE: different value than in comment
    {
        maskDAbort = TRUE;
    }

Part Number:CCSTUDIO

Tool/software: Code Composer Studio

Hi all

CCS v7 installation repeatedly fails. Tried deleting the installation folder and trying again. The error it returns says something about an error with the eclipse executable. I have attached the install log. Please help.

Thanks,.(Please visit the site to view this file)

Part Number:AM4376

Tool/software: Linux

Hi,

I have a question about AM437x touch screen controller.

My customer are planning to use 4-wire resistive touch pannel.
They are searching resistive touch screen linux driver for AM437x.

I guess Processor Linux SDK of AM437x doesn't include resistive touch screen driver for AM437x,
because capacitive touch screen panel are mounted on AM437x EVM not resistive touch screen.

Are there any resistive touch screen linux driver and user' guide  which we can refer to for AM437x?

best regards,
g.f.

Part Number:TMS320F28377S

Tool/software: Code Composer Studio

Hi Champion

My customer fail to install CCS v7 in Windows XP computer, want to confirm whether it is ok or not?

ERIC

Part Number:TMS320F28062F

Hi Champion,

My customer used two hall current sensors to sample 2 phase motor current.

But customer want to use the over modulation, wan to check the max value of USER_MAX_VS_MAG_PU .

ERIC

Part Number:AWR1642BOOST

I'm trying to capture the adc data, frame by frame now presently and dumping that code to a file using save memory in CCS, but now I want to capture adc data continuously and dump the adc data on to a file, so for that i need little reference please help me as I'm new to this hardware/software. 

Thanks,

Vinayak

Part Number:TMS320C6678

Hi,

I would like to know ,is there any way to transfer Ethernet data external memory using EDMA 

Regards

Part Number:TPS40056

Dear, All

Customers are conducting evaluations using TPS40056.
Their circuits are made variable output voltage by externally inputting voltage to EA_REF.

When observing the waveform at startup, they observed the following problem when VOUT is 1.5V or less.
- HDRV pulse width is about 50ns
- There is no dead time when LDRV rise.
Waveforms of interest are not observed in normal waveforms. It occurs only at startup.

Although the charge current to the output capacitor was suspected, the same waveform is observed even if the capacitance of the output capacitor is made extremely small.
Please tell me the cause and measures.

Thanks, Masami M.

Part Number:TMS320DM8168

Hi,

Does VOUT0 of DM8168 HDVPSS not support gamma correction?

I found only VOUT1 of DM8`48 HDVPSS support gamma correction in below e2e post: .

Is it similar on DM8168?

Thanks,

Part Number:TMS320F28379D

Tool/software: TI C/C++ Compiler

Hello there, 

i have started to use the LAUNCHXL-F28379D. 
The concept is to have all "IO things" on CPU1 while having all the algorithm on CPU2.
So the idea is to place all ADC results and all the other stuff in arrays which are then tied to global shared ram with a #pragma DATASECTION.
Of course the code in the main.cpp files of ech project are a bit different, but the #pragma DATASECTON´s are in the same order.
I have investgated the .map file and actually the arrays on the CPU´s don´t have the same order, see attachments at the bottom (mapfile, cmd files, pragma SECTIONS).
The projects are both running on optimization level -O2, have also tried the "off" condition with same result.
My question is how can i make sure the arrays are arranges equally on both CPU´s map files?
One idea could be to scramble the Global Shared RAM in chunks exactly the size of each array and define a name in the SECTION area of the map file. But this would mean some typing efford and more important a higher risk to forget something, whan an array gets changed in size...
Are there other approaches than that?

best regards, 
Jasson

(Please visit the site to view this file)

(Please visit the site to view this file)

(Please visit the site to view this file)

(Please visit the site to view this file)

Part Number:msp430f6435

Tool/software: Code Composer Studio

Hi,I used the following way for msp430 clock initialization .

***********************************************************************************

while(BAKCTL & LOCKBAK)                    // Unlock XT1 pins for operation
     BAKCTL &= ~(LOCKBAK);

  UCSCTL6 &= ~(XT1OFF);                     // XT1 On
  UCSCTL6 |= XCAP_3;                        // Internal load cap

  // Loop until XT1,XT2 & DCO stabilizes - In this case loop until XT1 and DCo settle
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag

**********************************************************************************

the program execution is not coming out of do_while loop which indicates that oscillator fault flag is not cleared .How to resolve this issue??

I have questions about LM5110.

Question 1.

  - In datasheet graph, frequency is ~1000kHz.

     (For example, Figure.3 and Figure 14.)

    Can we use this IC  at 2000kHz?

Question 2.

  - If we can use this IC at 2000kHz, how will Figure 7 and Figure 8 change?

Question 3.

  - Is there any important point when we can use this Ic at 2000kHz?

Best regards,

Takahiro Nishizawa

Part Number:CC1101-CC1190EM869RD

Tool/software: Linux

Hello! I designed a PCB based on your demo PC1101_CC1190EM 869MHz rev 2.1.0. I check on the spectral analyzer and do not really understand what is happening. There may be an error in the code when switching reception and transmission.

The board is not directly connected to the spectrum analyzer.

The board is installed on Raspberry Pi 3, using wiringPi SPI.

Software based on your Link2 example.

Base frequency: 869.524780 MHz

Xtal Freq: 27MHz

Data rate 38.4178 kBaud

Channel spacing: 207.641602 kHz

RX Filter BW: 105.468750 kHz

Deviation: 19.775391 kHz

Modulation: GFSK

TX Power (PA Table): 0xC0

Scheme

PCB 2-Layer

TOP Layer

BOTTOM Layer

Setting

uint8_t register_set_value[47] =
{
     0x07,  // IOCFG2              GDO2 Output Pin Configuration
    0x2E,  // IOCFG1              GDO1 Output Pin Configuration
    0x06,  // IOCFG0              GDO0 Output Pin Configuration
    0x0E,  // FIFOTHR             RX FIFO and TX FIFO Thresholds
    0xD3,  // SYNC1               Sync Word, High Byte
    0x91,  // SYNC0               Sync Word, Low Byte
    0xff,  // PKTLEN              Packet Length
    0x44,  // PKTCTRL1            Packet Automation Control
    0x05,  // PKTCTRL0            Packet Automation Control
    0x00,  // ADDR                Device Address
    0x00,  // CHANNR              Channel Number
    0x06,  // FSCTRL1             Frequency Synthesizer Control
    0x00,  // FSCTRL0             Frequency Synthesizer Control
    0x20,  // FREQ2               Frequency Control Word, High Byte
    0x34,  // FREQ1               Frequency Control Word, Middle Byte
    0x62,  // FREQ0               Frequency Control Word, Low Byte
    0xCA,  // MDMCFG4             Modem Configuration
    0x75,  // MDMCFG3             Modem Configuration
    0x13,  // MDMCFG2             Modem Configuration
    0x42,  // MDMCFG1             Modem Configuration
    0xF8,  // MDMCFG0             Modem Configuration
    0x34,  // DEVIATN             Modem Deviation Setting
    0x07,  // MCSM2               Main Radio Control State Machine Configuration
    0x30,  // MCSM1               Main Radio Control State Machine Configuration
    0x28,  // MCSM0               Main Radio Control State Machine Configuration
    0x16,  // FOCCFG              Frequency Offset Compensation Configuration
    0x6C,  // BSCFG               Bit Synchronization Configuration
    0x03,  // AGCCTRL2            AGC Control
    0x40,  // AGCCTRL1            AGC Control
    0x91,  // AGCCTRL0            AGC Control
    0x87,  // WOREVT1             High Byte Event0 Timeout
    0x6B,  // WOREVT0             Low Byte Event0 Timeout
    0xFB,  // WORCTRL             Wake On Radio Control
    0x56,  // FREND1              Front End RX Configuration
    0x10,  // FREND0              Front End TX Configuration
    0xE9,  // FSCAL3              Frequency Synthesizer Calibration                                 
    0x2A,  // FSCAL2              Frequency Synthesizer Calibration
    0x00,  // FSCAL1              Frequency Synthesizer Calibration
    0x1F,  // FSCAL0              Frequency Synthesizer Calibration
    0x41,       //RC Oscillator Configuration
    0x00,       //RC Oscillator Configuration
    0x59,        //Frequency Synthesizer Calibration Control
    0x7F,         //Production Test
    0x3F,       //AGC Test
    0x81,  // TEST2               Various Test Settings
    0x2D,  // TEST1               Various Test Settings
    0x09  // TEST0               Various Test Settings
};

 

Switching to transmission:

cc1101_StrobeCmd(SIDLE);
cc1101_StrobeCmd(SFTX);
cc1101_Write_BurstAccess(TX_FIFO, txBuffer, LENGHT_LENGHT_FIELD + txBuffer[0]); //DATA_LENGHT + CRC_LENGHT + LENGHT_LENGHT
cc1101_StrobeCmd(STX);

Switching to reception:

cc1101_StrobeCmd(SFTX);
cc1101_StrobeCmd(SIDLE);
cc1101_StrobeCmd(SFRX);
cc1101_StrobeCmd(SRX);

The transmission attempt is 5 times. On the screenshots of the spectral analyzer, you can see five transmissions. Why such a spread in frequency?

First send

Second

3

4

5

If you add a calligraphy before switching transitions, that is, like this:

Switching to transmission:

cc1101_StrobeCmd(SIDLE);
cc1101_StrobeCmd(SCAL);
cc1101_StrobeCmd(SFTX);
cc1101_Write_BurstAccess(TX_FIFO, txBuffer, LENGHT_LENGHT_FIELD + txBuffer[0]); //DATA_LENGHT + CRC_LENGHT + LENGHT_LENGHT
cc1101_StrobeCmd(STX);

Then the picture of the spectrum changes. I have not yet checked for data reception, but I'm still wondering if this is the correct behavior of the transmitter.

Here are all 5 transmission attempts.

How to properly switch between receiving and transmitting and correctly adjust the chip?

Part Number:CC2538

hi all,

how to send broadcast message to PAN network .

the TI example snippet code , i can't see the boardcast . have any one give Suggest?

//uint8 zclSampleFireDetector_IAS_CIE_Address[8] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };

//#define AF_BROADCAST_ENDPOINT              0xFF
//#define SAMPLEFIREDETECTOR_ENDPOINT            17


    // zone enrollment request to CIE, only perform after writing cie address attribute value
    afAddrType_t zclCIE_Addr;

    zclCIE_Addr.addrMode = (afAddrMode_t)(Addr64Bit);
    osal_memcpy(zclCIE_Addr.addr.extAddr, zclSampleFireDetector_IAS_CIE_Address, Z_EXTADDR_LEN);
    zclCIE_Addr.endPoint = AF_BROADCAST_ENDPOINT;

    zclSS_IAS_Send_ZoneStatusEnrollRequestCmd( SAMPLEFIREDETECTOR_ENDPOINT,
                                               &zclCIE_Addr,
                                               zclSampleFireDetector_ZoneType,
                                               22, 0, 1);

ZStatus_t zclSS_IAS_Send_ZoneStatusEnrollRequestCmd( uint8 srcEP, afAddrType_t *dstAddr,
                                                     uint16 zoneType, uint16 manufacturerCode,
                                                     uint8 disableDefaultRsp, uint8 seqNum )
{
  uint8 buf[PAYLOAD_LEN_ZONE_ENROLL_REQUEST];

  buf[0] = LO_UINT16( zoneType );
  buf[1] = HI_UINT16( zoneType );
  buf[2] = LO_UINT16( manufacturerCode );
  buf[3] = HI_UINT16( manufacturerCode );

  return zcl_SendCommand( srcEP, dstAddr, ZCL_CLUSTER_ID_SS_IAS_ZONE,
                          COMMAND_SS_IAS_ZONE_STATUS_ENROLL_REQUEST, TRUE,
                          ZCL_FRAME_SERVER_CLIENT_DIR, disableDefaultRsp, 0,
                          seqNum, PAYLOAD_LEN_ZONE_ENROLL_REQUEST, buf );
}

z-stack-example-apps(IAS Zone)

git.ti.com/.../z-stack-example-apps

Thank you for considering my request

Part Number:CC3200

Are there any methods to protect the CC3200 external flash from readback?

Part Number:CC3200

hey,

I have the cc3200 launchpad and I am trying to get an intterupt on a rising edge on GPIO_PIN_4 but without a success. The intterupt is too sensitive and even if I connect it to Ground it gets the intterup.

Can someone please help me with that?

that is my code :

void isrCheck1()
{
Report("Interrupt on GPIO 1.4 \n\r");
}

main()

{

GPIOIntTypeSet(GPIOA1_BASE,GPIO_PIN_3,GPIO_HIGH_LEVEL);
GPIOIntTypeSet(GPIOA1_BASE,GPIO_PIN_4,GPIO_HIGH_LEVEL);
GPIOIntRegister(GPIOA1_BASE,isrCheck1);

IntEnable(INT_GPIOA1);
HWREG(0x4402E144) |= 16 << 2;
GPIOIntTypeSet(GPIOA1_BASE,GPIO_PIN_4,GPIO_HIGH_LEVEL);
GPIOIntEnable(GPIOA1_BASE,GPIO_INT_PIN_4);

}

Ohad

Part Number:MSP430F2132

After the BSL entry, I send an error Password to the BSL,  I think that the ACK shoud be 0xA0, but it actually is 0x90, why? And how to judge the Password whether it is correct?

such as, I have downloaded a code to the MSP430F2132, then I download the code the second time,I use the command as follows:

80 10 24 24 E0 FF 20 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 9B 34

the BSL returns 0x90

why not the 0xA0?