Part Number:MSP430F5529
Team,
I am trying to generate a OWM sine wave via lookup table, but I am seeing a weird artefact in the wave. Here is the code I am using to generate the waveform:
#include <msp430.h>
void setClocks();
void PWMRegsetup ();
unsigned int i=0, j=0; //counters for for loop
const unsigned int sinTable[] = {512,562,611,660,707,753,796,836,873,907,937,963,984,1001,1013,1021,1023,1021,1013,1001,
984,963,937,907,873,836,796,753,707,660,611,562,512,461,412,363,316,270,227,187,
150,116,86,60,39,22,10,2,0,2,10,22,39,60,86,116,150,187,227,270,316,363,412,461,512};
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Disable WDT
PWMRegsetup();
setClocks();
TBCTL = TBSSEL_2+MC_1; // SMCLK, upmode
TBCCR0 = 1024-1; // PWM Period indicates a 10-bit DAC
TBCCTL0 = CCIE; // TRCCR0 interrupt enabled
TBCCTL6 = OUTMOD_7; // CCR3 reset/set
while(1){
__bis_SR_register(LPM0_bits + GIE); // CPU off. Used for ISR
__no_operation(); // For debugger
}
}
// FUNCTIONS //
// Timer B0 interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMERB0_VECTOR
__interrupt void TIMERB1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMERB0_VECTOR))) TIMERB1_ISR (void)
#else
#error Compiler not supported!
#endif
{
//Output a Sine Wave PWM on pin P3.6
TBCCR6 = sinTable[j]; // CCR3 PWM duty cycle
j++;
if(j>=64)
j = 0;
}
void setClocks(void)
{
UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
// Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation
UCSCTL2 |= 762; // Set DCO Multiplier for 8MHz
// (N + 1) * FLLRef = Fdco
// (762 + 1) * 32768 = 25MHz
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 25 MHz / 32,768 Hz = 781000 = MCLK cycles for DCO to settle
__delay_cycles(781000);
}
void PWMRegsetup (void)
{
P3SEL |= BIT6; // P3.6 option select
P3DIR |= BIT6; // P3.6 output (TB6)
}
I'm wondering if I am calling something in the ISR routine incorrectly? Any advice would be appreciated.
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