Hi
we are using cc1101 for "mics" band which is defined to be 403Mhz.
I saw in the cc1101EM schematics the coupling network uses for 433Mhz and 915Mhz but my question is:
how can I calculate (or that you can calculate) the component values for 403Mhz coupling network?
thanks in advanced,
Regards,
Hi , i am a so newbie ...I have a trouble problem on DM8164....Now ,I have achieved run a video via VGA(display3) on DM8164 (linux) by this code:
devmem2 0x48140894 w 1
devmem2 0x48140898 w 1
devmem2 0x48140724 w 4
echo 0 > /sys/devices/platform/vpss/display3/enabled
echo component,rgb888 > /sys/devices/platform/vpss/display3/output
echo 1 > /sys/devices/platform/vpss/display3/enabled
gst-launch filesrc location=/usr/share/ti/data/videos/dm816x_1080p_demo.264 ! 'video/x-h264' ! h264parse access-unit=true ! omx_h264dec framerate=24 ! gstperf ! omx_scaler ! "video/x-raw-yuv,width=1920,height=1080" ! v4l2sink sync=false device=/dev/video2
I want to run a video and display via HDMI and VGA simultaneously.
How can Ido？please help.
Dear team,
Customer use only 2 channel of DS100DF410. Then customer asked us is there better channel combination to improve performance when customer use only 2 channel(ex. ch0 and ch3).
I think it is better to use ch0 and ch3, and power down ch1 and ch2.
Is my understand correct?
Regards,
Hiroshi Kezuka
Good morning,
i'm using CCS v5.3 for DSP C6457.
Actually i'm using the Log_infoX() in order to notify the program execution.
Actually i have the necessity to differentiate the Logger. (as for the LOG_printf(&log1...LOG_printf(&log2, in the CCS v3.3).
Is possible to have multiple TAB in order to differentiate the program Log and collect them?
Thanks in advance.
Fabio
Hi all,
the status bits for exception channel A and B seem to be swapped in the product data sheet and there is no errata on this. While developing our application we found that the status bit for exception channel A is set when an exception occurrs that maps to channel B (and vice versa). There is also a related post from 2009, where someone complained he could not clear the exception bit (only with a full reset). Since we swapped the meaning of the status bits, everything works as expected, i.e. it is also possible to clear the status bit when the related exceptions are cleared (without device reset).
Is anybody using these status bits?
Can anybody please confirm this as an error in the CC2520 data sheet (December 2007)?
Best regards
Hi,
help me in programming the registers of an IC using GP I/O of TMS320C6678. Please suggest me a example program and related data link.
Thank you.
Hi,
Need help in programming the registers of an IC through GP I/O of TMS320C6678. Please suggest me a example program and related data link.
Thank you.
Hello,
I am trying to check the MIBSPI and DMA function on TMS570LS3137 device.
On my board MIBSPI1, two slaves are connected.
And my RTOS generates two periodic tasks (1ms task and 10ms task).
Now, I would like to carry out SPI communication with SLAVE1 by 1ms task,
andwith SLAVE2 by 10ms task.
Furthermore, in order to reduce the overhead of CPU,
I would like to use RX DMA and TX DMA with MIBSPI1.
The conditions of MIBSPI1 communication are as follows.
"MASTER(TMS570) <-> SLAVE1"
(The number is variable and it may change for every cycle. It is decided in the 1ms task).
"MASTER(TMS570) <-> SLAVE2"
(The number is variable and it may change for every cycle. It is decided in the 10ms task).
Others are the same conditions as SLAVE1.
The priority of SLAVE1 is higher than SLAVE2, and the communication with SLAVE2 can be interrupted
by the communication with SLAVE1.
I think there are three points which make the problem not easy.
1. The number of data transmission is variable for every cycle.
2. In the worst case, the send data size is over MIBRAM size.
(There are 128 buffers in MIBRAM, and one buffer can contain 16bits data for each of transmit and receive.
so MIBRAM can contain up to 2048 bits transmit/receive data .
However, I would like to send 3200 bits (32-bit * 100-word) data in the case of maximum transmission. )
3. Cooperation with TX/RX DMA.
Could you please tell me how it can be resolved?
The data sheet for my LM3S1968 says that core registers, such as the general purpose registers, are not memory mapped and are accessed by register name. In this case, I want to read General Purpose Register 5, and the data sheet says that the name of that register is "R5." When I write the name R5 in my code, the compiler does not recognize it. I'm including the header file for the board, but it is no help.
Will somebody please be nice enough to write a code example that shows how to read General Purpose Register 5 by using its name (not a mapped address) using C?
hi,
When i set the coordinator's zgApsUseExtendedPANID to be {0x12,00,00,00,00,00,00,00 }, and router's to be all 0.
Then when the router joins into the network, how to get the extended pan ID at the application layer?
Thanks!
概要
このユーザーズ・ガイドは、テキサス・インスツルメンツから提供している開発サポート・ツール “フラッシュ・エミュレーション・ツール” (FET) のキットと評価用ボード (MSP-EXP430xxxxx)の説明と、ハードウェア用ドライバ・ソフトウェアのインストール方法を紹介しています。
FET は、超低消費電力マイコン MSP430 用プログラム開発ツールで、USB接続により、とても簡単に使うことができます。
各ツールがサポートできるデバイスのリスト、4 線式または、2 線式JTAG の接続回路例、ツールの回路図とパターン図を掲載しております。
開発時のリファレンス資料としてお使いください。
また、セクション1.18 では、ソフトウェアの開発方法や、MSP430の仕様の詳細についての関連資料を案内しています。 。
| Document Title | Size (KB) |
 MSP430(tm) Hardware Tools User's Guide (slau278n.pdf, 6.84 MB) | 1539 |
関連リンク
I have a TMS320VC5416 DSP developed on TMDSDSK5416 development kit, and i'm using a daughterboard interface to communicate it trough UART serial connection.
I need a smaller (much smaller than the TMDSDSK5416) development kit which allow me to connect the DSP directly trough UART interface.
I'll be glad to hear about solutions.
Best regards,
Amit Hadar
The TPS65910A3 datasheet recommends 1.2k pull-ups on SCL & SDA; whereas, the AM335x Schematic Checklist specifies 4.7k.
Please clarify this discrepancy.
Regards,
Russ
Hello,
OMAP-L138 Reference Manual says that TA precedes the Async EMIFA operation.
Could you please explain in plain English how this feature helps slow down access to a slow peripheral?
If TA cases leading delay, then I suspect SW cannot assign a prolonged TA to the peripheral with slow OE-to-databus-High-Z response time. What am I missing here?
Many thanks,
Milan
Hi,
I am using eZdspTM F2812 Board and CCS Version3.1 for doing my project. I had connected the target and run the program without any errors.
I don't know why, but now i am not able to connect to the target. When i try to connect the target, i got an error message like this,
"Error connecting to the target:
Error 0x80000200/-1031
Fatal Error during: OCS,
Device driver: Problem with the Emulation Controller.
It is recommended to RESET EMULATOR. This will disconnect each
target from the emulator. The targets should then be power cycled
or hard reset followed by an emureset and reconnect to each target.
Sequence ID: 0
Error Code: -1031
Error Class: 0x80000200
I/O Port = 378
Board Name: F2812 eZdsp
Cpu Name: cpu_0
Abort: Close Code Composer Studio.
Retry: Try to connect to the target again.
Cancel: Remain disconnected from the target
Diagnostic: Run diagnostic utility."
Can you please help me to solve this error?
With regards
Devisree Sasi
Hi All,
I am using XDS100v2 from Spectrum Digital with OMAP-L138. I am receiving following error when trying to debug application:
Error connecting to the target:
(Error -150 @ 0x0)
This utility failed to operate the adapter for a custom emulator.
The adapter returned an error for unknown reasons.
(Emulation package 5.0.520.0)
Does somebody know what does this error means?
Hi all,
I have a doubt in pinmux of signal GPMC_AD8 to GPMC_AD15.
Regards,
Ebin
Hi, I am trying to communicate UART on the Stellaris cortex-M4 LM4F232. In the example “uart_echo”, it didn’t use the following f(x):
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
But if I use the pin PE4 and PE5 as U5RX and U5TX，do I must use the GPIOPinConfigure()?I am pasting my code below:
When I compile this code by MDK-Keil, there are two errors, my question is:
I have put the “pin_map.h” into my project as Fig.1, and the “pin_map.h” had defined the UART port as Fig.2. Why does it point out the U5RX andU5TX are undefined
I'll appreciate if anyboday can look at this issue for me.
DM8148 EVM with the lasted SDK ezsdk_5_05_02_00_dm814x, the video capture by gst-launch dosn't work. I tried many gst-launch v4l2src xx with video format fourcc YUY2, always get output like: GstV4l2Src:v4l2src0: Could not negotiate forma. If change the format fourcc to something else like GRAY, error will be: WARNING: erroneous pipeline: could not link v4l2src0 to omxbasectrl.
Firmware call in load-hd-firmware.sh under /etc/init.d, the line to load v4l2 firmware like:
firmware_loader $HDVPSS_ID /usr/share/ti/ti-media-controller-utils/dm814x_hdvpss_v4l2.xem3 start -i2c 0
And at the bootup phase, get some error like:
Loading HDVPSS Firmware (V412)
FIRMWARE: Memory map bin file not passed
Usage : firmware_loader <Processor Id> <Location of Firmware> <start|stop> [-mmap <memory_map_file>] [-i2c <0|1>]
===Mandatory arguments===
<Processor Id> 0: DSP, 1: Video-M3, 2: Vpss-M3
<Location of Firmware> firmware binary file
<start|stop> to start/stop the firmware
===Optional arguments===
-mmap input memory map bin file name
-i2c 0: i2c init not done by M3, 1(default): i2c init done by M3
FIRMWARE: isI2cInitRequiredOnM3: 0
FIRMWARE: Default memory configuration is used
Firmware Loader debugging not configured
Default FL_DEBUG: warning
Allowed FL_DEBUG levels: error, warning, info, debug, log
MemCfg: DCMM (Dynamically Configurable Memory Map) Version : 2.1.2.1
FIRMWARE: 2 start Successful
VPSS_FVID2: M3 firmware version 0x1000145 is newer,driver may not work properly.
omap_i2c omap_i2c.3: timeout waiting for bus ready
I2C: Transfer failed at vps_ti814x_select_video_decoder 188 with error code: -110
Configuring fb0 to LCD
HDMI W1 rev 4.0
HDMI CEC Spec version 1.2
I2C No Ack
Please advise!
hi
i was trying to understand sv04
there I did wrote copied ti function and gave them name with ch2
ret = _ALG_allocMemory_ch2(memTab, n);
if ( ret == TRUE)
{
alg = (IALG_Handle) memTab[0].base;
alg->fxns = fxns;
// t_errno = 8989;
// return NULL;
// if ((ret = fxns->algInit(alg, memTab, p, params)) == IALG_EOK)
if ((ret = fxns->algInit(alg,memTab,NULL, NULL)) == IALG_EOK)
{
t_errno = -999;
return NULL;
return (alg);
}
t_errno = 9090;
return NULL;
Mine objervation over here were i do get 8989 error but dont get 9090 and 999 error.
i feel like there is some kind of segmentation fault in alg_init
this is the code snippet from siuvctmemmgr.c
Sorry guys i dont have any emulator, working on advantech pcie 8581, yesterday i implemented provision for an intiger through mailbox
so errorno is all what i have for debuugiing
