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[TDA4M] Could I get a caffe model and prototxt of 'MobileNet-1.0V2 + ASSP'.

November 4, 2019, 6:58 pm
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Hi

Actually, I have a problem about image size. When I used a big image, it was fail on EVM, but it was OK on HOST.

I tried with a small image, and then It was OK on EVM. It looks like there is relation in image size.

So, I would like to ask a caffe model of TI samples.

As you know, Ti used tidl_net_onnx_tiadsegNet_v2 for semantic segmentation. But I couldn't get a caffe model and prototxt of that network.

If I have those files, I think I can get more information through importing.

I was wondering If I could get a caffe model and prototxt of 'MobileNet-1.0V2 + ASSP'.

Best regards

Yongsig.

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HD3SS3412A: PCIE switch HD3SS3412 compatibility with Intel Broadwell DE/ Hwwitt lake

November 4, 2019, 7:11 pm
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Part Number: HD3SS3412A

I am looking for a PCIE multiplexer.. This device will be interfacing the Intel CPU root port ( Broadwell DE / Hewitt lake)  The downstream device will be FPGAs.

I got details of the below device from TI portal.

http://www.ti.com/lit/ds/symlink/ts2pcie412.pdf

 

I am looking for 8 channel device similar to TS2PCIE412.  looks like 8Ch device is not available  TS2PCIE412 or   which one   Is  commonly use and compatible with Intel CPU like Broadwell DE / Hweiit lake ?

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DAC61416: Voltage output problem

November 4, 2019, 7:01 pm
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Part Number: DAC61416

Hello：

I tried to output a voltage of 0 to 20V with DAC61416. I used MC9S12 microcontroller to communicate with DAC61416 via SPI.When I select the output range is -5 V to +5 V 、 -10 V to +10V、-20 V to +20V or -2.5 V to +2.5 V ,the output voltage is only 1.4V. When I select the output range is 0V to +5V 、 0V to +10V 、0V to +20V or 0V to +40V ,the output voltage is 0v. I am sure there is no problem with SPI communication.

This is the register configuration：

DrvDacWriteReg(DACRANGE2R_ADDR, 0x2222);
 DrvDacWriteReg(DACRANGE3R_ADDR, 0x2222);
 DrvDacWriteReg(SPICFGR_ADDR, 0x0A84);
 DrvDacWriteReg(GENCFGR_ADDR, 0x3F00);
 DrvDacWriteReg(DACPWDWNR_ADDR, 0x0000);
 DrvDacWriteReg(BRDCFGR_ADDR, 0xFFFF);
 DrvDacWriteReg(BRDCASTR_ADDR, 0xFFFF);

Please let me know why this problem occurs or if you can help me directly with this, it would be a great help.

Thanks and Regards,

chaogang zhu

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UCC21222: Higher Vdd

November 4, 2019, 7:16 pm
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Part Number: UCC21222

Dear Team,

The original main source voltage max is 24V.
UCC21222 driver max only 20V.

The voltage steady-state designed to drive the SIC MOS is 18V, which is quite close to 20V.
I am afraid of overvoltage stress during the transient.

But we don't have a higher Vdd device, right?

BR

Kevin

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CCS/AWR1843: How to communicate MSS and BSS?

November 4, 2019, 7:19 pm
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Part Number: AWR1843

Tool/software: Code Composer Studio

Dear 

I study the Ti document(AWR1xxx Radar). I find out the  AWR16xx Software Architecture as below:

The Figure shows BSS communicate with MSS by MailBox. Is there a reference code about BSS communicate with MSS by Mailbox?

Since the document shows a lot of APIs need that  MSS  send messages to BSS by MailBox to use.

Thank you.  

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CC2652R: Non-connected TOF

November 4, 2019, 7:20 pm
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Part Number: CC2652R

Hi Team,

In CC2640R2F SDK 3.20, there are single TOF examples----tof_initiator/tof_responder, Which can implement non-connected TOF. In the latest SDK,there are only RTLS examples, is non-connected TOF still supported? If yes, please provide some advice, thanks.

BR,

Viki Shi

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XIO2001: D3 in S0 and entry C10?

November 4, 2019, 7:21 pm
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Part Number: XIO2001

Hi Team,

Please kindly help if XIO2001 can support these power saving stage.

1. Could you please help check if XIO2001 can support D3 in S0 ?

2. May I know if  TI have any success experience about XIO2001 entry C10 with XIO2001 IC ?

Thanks

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PROCESSOR-SDK-TDAX: Whether TDA4x timer IO can mapping to any internal 1024 internal timer module?

November 4, 2019, 7:25 pm
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Part Number: PROCESSOR-SDK-TDAX

Hi Experts:

We need connect 12 ultra sonic sensor capture function to TDA4x. Those sensor need use timer PWM capture function to detect the PWM pulse wide change.

TDA4x have 7 timer_io pins at main domain and 9 MCU_Timer_io pins at MCU domain.

At TRM 12.10.3.1 introduce that it contain 30 timer module at TDA4x. In-order to avoid conflict to software used Timer, whether those 30 timer , any timer module can mapping to MCU/Main domain timer IO or it have some limited?

Best Regards!

Han Tao

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DS90UB954-Q1: Question for CSI-2 setting

November 4, 2019, 7:35 pm
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Part Number: DS90UB954-Q1

Hi Team,

My customer asked CSI-2 setting for below specific case.

Could you check if below settings are reasonable to have sufficient bandwidth?

<<  System requirement >>

1. configuration : CMOS sensor + 953 + 954 (single 953 is connected)

2. streaming data : 1920x1080x60fps, 12bit/pixel (Raw12bit)

     --> 1.64Gbps with Blanking rate =1.1

3. max 1.5Gbps for ISP lane

<< DS90UB954 configuration >>

1. For FPDLINK setup for non-synchronous CSI-2 mode

set FPD3_MODE = "00",

REFCLK = 25MHz(from xtal oscillator)

2. For CSI-2 setup

From Table 13, to set CSI frequency less than 1.5Gbps with REFCLK=25MHz,

(1) CSI_PLL_CTL[1:0] has to be set as "00"

(2) IND_ACC_CTL[5:2] =  "0111"

(3) IND_ACC_ADDR = 0x08

(4) IND_ACC_DATA[7:6] = "11" (csi pll divider setting = 52)

(5) CSI_LANE_COUNT = "10" (2 lane)

With this setting, I expect 954 has 1.3Gbps x 2 lane capability.

Best regards,

Nobuo

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SECDEVTOOL-OMAPL138C6748: M1OMAPL138EZCER

November 4, 2019, 7:37 pm
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Part Number: SECDEVTOOL-OMAPL138C6748

I am using M1OMAPL138EZCER in my current product but have difficulty to identify which DSP core that I am using.

May I know where and how can I find out this piece of information?

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TPS2663: More Appropriate Device for OVP/OCP/OTP

November 4, 2019, 7:40 pm
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Part Number: TPS2663

Hi All,

My customer would like to find the OVP/OCP/OTP below.

OVP:ˋ42Vmax 

OCP:10Amax

OTP:75 degree C→shut down ; 45 degree C→recover

Could you help find the more appropriate solution by e-fuse?

Thanks.

Regards,

Roy

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AM3352: Vtt Terminator

November 4, 2019, 7:49 pm
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Part Number: AM3352

Dear Team,

What is the difference without the VTT terminator here?

BR

Kevin

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TDA4 High speed interface layout

November 4, 2019, 7:49 pm
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Hello,

Regarding the High speed differential signal routing guidance: TDA4 Spec suggest reference SPRAAR7H this document, but I have some question need your help to clarify.

1. Display port of impedance and max trace length

2. CSI of impedance and max trace length

3. DSI of impedance and max trace length

4. RGMII of impedance and max trace length

5. CAN of impedance and max trace length

6. OSPI  of impedance and max trace length

Best Regard,

Tony

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DS90UB948-Q1: Asking for the recommendation on DS90UB948/949 setting

November 4, 2019, 7:52 pm
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Part Number: DS90UB948-Q1

Hi Team,

Customer is designing DS90UB948/949. And would you please help for the following questions.

Q1. Will 948/949 detect and determine the input source format and LCD panel are match or not? Then, the LCD can normal display under the 948 MODE_SEL0 set to corresponding proper setting.

Q2. For case 2, do customer need to adjust 948/949 output resolution?

 

Here are the experiment on customer’s board. 

case 1. Customer used HDMU pattern generator to generate the signal that matching the LCD panel spec as below.

Customer need to set MODE_SEL0 to1.241V

LCD panel can display normal.

Case 2. Customer used Notebook(1366 X 768) and android phone(un-known resolution) to output the HDMI signal

customer need to set ODE_SEL0 to 2.642V or 3.3V

LCD panel can be partial display normal.

In case 2, the display resolution is not correct form the LCD panel. 

Here are the original Notebook and Android phone content on notebook and phone.

However, after 949 to 948, the content showed on LCD panel are as below.

For notebook case, the content width is becoming wider. For the phone, it the scale on length and width are not as same as phone content.

Here are the block diagram, schematic and LCD panel spec.

txn.box.com/.../yxzhj85v2kllno1uudo50f9ytdhg4v34

BR,

SHH

 

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BQ27750: BQ27750

November 4, 2019, 8:00 pm
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Part Number: BQ27750

Hi,

We are trying to connect  a BQ27750 using bqstudio, EV2400,7802.1750_0_04-bq27750.bqz file.The following picture is the message box that pops up when BQ27750 is connected.

Click OK button bqstudio can connect to the chip correctly.We can also read and write registers correctly.My question is whether this warning message has any effect.

When we try to export DFFS file,The following message pops up.

Thank you for your attention

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CC2640R2F-Q1: Command Line Interface for CC2640R2F

November 4, 2019, 8:04 pm
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Part Number: CC2640R2F-Q1

Hi,

I am windows 10 user. I have flash programmer 2 (1.8.0) on my device. How can I use a command line interface of this programmer?

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CCS/TMS320VC5416: C HEADER file creation from .out file

November 4, 2019, 8:11 pm
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Part Number: TMS320VC5416

Tool/software: Code Composer Studio

I want to create "C" header file from .out file. I found this application note "SPRAA64 − November 2004::Using OFD Utility to Create a DSP Boot Image" on ti website.However the link mentioned in the first half of the first page of note is not functional. The non working  link is " http://www−s.ti.com/sc/psheets/spraa64/spraa64.zip".

can somebody help in downloading the file to be able to create  c header or source file  for HPI boot table??

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TPS54260: RT / CLK input waveform

November 4, 2019, 8:13 pm
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Part Number: TPS54260

Hi

My customer has question.

The customer inputs an external clock to RT / CLK. (External clock = 3.3V)
When checking the RT / CLK waveform with the TPS54260 activated, the clock has no margin against the threshold (2.2V).
Increasing the external clock voltage is not possible due to the possibility of exceeding the rating.
Is there no problem in this state?
If there is a problem, I think I need to adjust the external constant. Is there a suitable constant?

(Please visit the site to view this file)

Best Regard

T Kishi

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LP8863-Q1: About Apply to VOUT from external voltage

November 4, 2019, 8:21 pm
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Part Number: LP8863-Q1

Hi Team,

 

We would like to apply to VOUT from external voltage(around 12V) at LP8863 is disabled.

Because, we would like to use LED current more than 150mA(LP8863 can’t use) as needed.

Case1: When LP8863 is enabled and SW1 & SW2 is OFF, LED current is less than 150mA

Case2: When LP8863 is disable and SW1 & SW2 is ON, LED current is more than 150mA

 

Therefore, we study the following dual input SEPIC circuit.

Could you please let us know if you have any concern?


 

Regards,

Hide

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LM5116: Generate Sync out signal

November 4, 2019, 8:28 pm
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Part Number: LM5116

Hi Sir,

I wanted to use LM5116 in master-slave configuration. The first LM5116 should be able to generate sync in signal for the second LM5116. So that no external oscillator circuit is required.

Could you suggest the configuration and supporting document to use LM5116 in master slave configuration.

Thanks and regards,

Nesh

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