Part Number: TMS320LF2407A
The datasheet states “The x240xA DSPs do not include boundary scan. The scan chain of these devices is useful for emulation function only.”
Does this mean that Boundary Scan testing of downstream devices in the JTAG chain can’t be done through the tms320lf2407a JTAG interface?
Since it does not support boundary scan, I guess it would need a bypass mode in order to do this. Does it have this bypass mode?
Hi,
Do we have PFC single phase dual boost bridgeless to propose to customer for new designs? Write also me in private for any roadmap we might have.
Many Thanks,
Antonio
Part Number: LM5050-1
Hi Guys
Our customer is using our LM5050, their system: typical 48V, MAX 54Vout; But there will be a surge voltage ~100V about 10us; not sure accurate value; But they are concern our datasheet:
Our device exposure to max conditions for extended periods may affect device. So typically how much voltage value do you test to prove this explanation? 110V for 1us? or some other value for several seconds? Customer want to design a Absorption energy protection circuit. So need our this test data. if you have no, do you know how much voltage will affect our device?
Thanks
-Pengfei
So
Part Number: TPS61089
Hi team,
A customer is asking for the design files of TPS61089. Can we provide Altium files (schematic symbol/footprint/3D file)?
Thank you,
Franz
Hi,
Do we have LLC IC 2kW 24V 70A to propose to customer for new designs? Write also me in private for any roadmap we might have.
Customer targets are;
Increase equipment efficiency
Do not use DSP but just analog solutions
It is a coupled question with: https://e2e.ti.com/support/power-management/f/196/t/851645
Many Thanks,
Antonio
Part Number: TPS650861
Hello,
I'm testing TPS650861 for our new project.
I need to get 3 voltages from BUCK1, 2 and 6:
- Fixed 3,3V
- Fixed 5V
- Digitally regulated 2,5...5V
My idea is to get:
1. Fixed 3,3V from BUCK6 - because of internal VTT LDO feedback, it's output cannot be higher then 3,6V so this is the option for 3,3V.
2. Fixed 5V from BUCK1 - using the Ext FB option with external resistors
Question: Am I correct that when Ext FB option is selected, then there is no possibility to change the output voltage using VID reg. value?
3. Regulated 2,5...5V from BUCK2 - I added a serial resistors on the FBVOUT2 and I measured that there is 8,2uA current flowing into the feedback pin. From there I calculated a serial resistor of 174k and that gives me the desired voltage range.
Question: My question is about the structure of the FBVOUT2 input. Is there a simple resistor divider at that input connected to a comparator? Is my solution OK or may it ruin some feedback characteristics??? Can you tall me about the input structure of that pin so that I would know what I'm doing?
I really hope this will work as this PMIC would be perfect for our system.
Kind Regards,
Jacek Renkas
Part Number: CC3220MODA
Hi
Our customer has question of APP_EVENT DISCONNECT.
I attach logs.
(Please visit the site to view this file)
The both logs offer "Device disconnected from the AP on an ERROR".
In left logs, it succeeds to reset and reboot the system using platform reset.
In right logs, it repeats "Device disconnected from the AP on an ERROR" with 204 and 208 alternately after using platform reset.
I don't know why there are differences between upper two cases.
Could it be possible that there are differences in behavior after platform reset depending on the connecting router?
If yes, could you tell me the router function that will cause to above differences in behavior?
BestRegards
Part Number: ADS1299EEGFE-PDK
HI Ti team :
CTM buy a ADS1299 demo board ,Now they want to use demo to see the test results, but there is no matching signal acquisition cable.。Where can I buy the signal acquisition cable that matches the ADS1299 demo board?
Hello All
I have some problem with developmnet and debugging application where the CM control USB Periphery.
I can not to see the registers of USB on the Cortex_M4_0 side. I can see this one only on the C28xx_CPU1 side.
Besause it is appiared only on the C28xx_CPU1 side, on the Cortex_M4_0 side it is absent.(For example CANA and CANB registers I can abserve on the both sides)
So statement HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD,
which is fulfilled on the Cortex_M4_0 side does not make any effect to the registers. Or at least I do not observe any changing on the C28xx_CPU1 side.
The Clock gating is configured properly on the both sides and PALLOCATE0 register configured to allocate USB_A to CM side.
Can somebody help me ?
Best regards
Andrii Shevchuk
Part Number: INA286
Hi Guys
Our customer will use our INA286 as high side current sense. Typical common mode voltage is 48V. But we have some questions:
1. If we power off our device, but the main power voltage is high voltage 48V. So at this no power supply conditions, do you think whether it will damage our device when power up INA286 or operation?
2. If we have no power supply, how much quiescent current will our device have? 900uA? 500uA? or lower?
Thanks
-Pengfei
Part Number: TCA9539
Hi Sir,
If the TCA9539 I/O pin has 10K ohm pull low resistor as below, how is the Rds on for the TCA9539?
Thanks
Part Number: TUSB1046-DCI
Hi Team,
According to this App. Note, the maximum pre-channel trace/ post-channel trace for USB3.1 Gen 2 supported by the TUSB1046A-DCI is 6 inches/ 4 inches.
What about for DP1.4 signals? What are the maximun pre-channel and post-channel trace supported by this device?
Thanks!
Roy Hsu
Part Number: TMS320F280049
Hi expert,
I am tring to lock F280049 with the provided asm file and cmd file but it seems goes to wrong location. Here is the asm file I modified and memory content.
It seems not to the right position, what happens here?
Attached the cmd and asm here.
CMD:
/* this linker command file is to be included if user wants to use the DCSM
* feature on the device DCSM means Dual Zone Code Security Module. This
* linker command file works as an addendum ot the already existing Flash/RAM
* linker command file that the project has.
* The sections in the *_ZoneSelectBlock.asm source file is linked as per the
* commands given in the file NOTE - please note fill=0xFFFF, this helps if
* users include this file in the project by mistake and doesn't provide the
* needed proper *_ZoneSelectBlock.asm sources.
* Please refer to the Blinky DCSM example for proper usage of this.
*
* Once users are confident t`hat they want to program the passwords in OTP, the
* DSECT section type can be removed.
*
*/
MEMORY
{
PAGE 0 : /* Program Memory */
/* BANK0 */
/* B0 Z1 OTP. LinkPointers */
B0_DCSM_OTP_Z1_LINKPOINTER : origin = 0x78000, length = 0x00000C
/* B0 Z1 OTP. GPREG1/GPREG2 */
B0_DCSM_OTP_Z1_GPREG : origin = 0x7800C, length = 0x000004
/* B0 Z1 OTP. PSWDLOCK/RESERVED */
B0_DCSM_OTP_Z1_PSWDLOCK : origin = 0x78010, length = 0x000004
/* B0 Z1 OTP. CRCLOCK/RESERVED */
B0_DCSM_OTP_Z1_CRCLOCK : origin = 0x78014, length = 0x000004
/* B0 Z1 OTP. GPREG3/BOOTCTRL */
B0_DCSM_OTP_Z1_BOOTCTRL : origin = 0x7801C, length = 0x000004
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
/* B0 Z1 OTP. Z1 password locations / Flash and RAM partitioning */
B0_DCSM_ZSEL_Z1_P0 : origin = 0x78020, length = 0x000010
/* B0 Z2 OTP. LinkPointers */
B0_DCSM_OTP_Z2_LINKPOINTER : origin = 0x78200, length = 0x00000C
/* B0 Z2 OTP. GPREG1/GPREG2 */
B0_DCSM_OTP_Z2_GPREG : origin = 0x7820C, length = 0x000004
/* B0 Z2 OTP. PSWDLOCK/RESERVED */
B0_DCSM_OTP_Z2_PSWDLOCK : origin = 0x78210, length = 0x000004
/* B0 Z2 OTP. CRCLOCK/RESERVED */
B0_DCSM_OTP_Z2_CRCLOCK : origin = 0x78214, length = 0x000004
/* B0 Z2 OTP. GPREG3/BOOTCTRL */
B0_DCSM_OTP_Z2_BOOTCTRL : origin = 0x7821C, length = 0x000004
/* DCSM Z1 Zone Select Contents (!!Movable!!) */
/* B0 Z2 OTP. Z2 password locations / Flash and RAM partitioning */
B0_DCSM_ZSEL_Z2_P0 : origin = 0x78220, length = 0x000010
/* BANK1 */
/* B1 Z1 OTP. LinkPointers */
B1_DCSM_OTP_Z1_LINKPOINTER : origin = 0x78400, length = 0x00000C
/* DCSM B1 Z1 Zone Select Contents (!!Movable!!) */
/* B1 Z1 OTP. Flash partitioning */
B1_DCSM_ZSEL_Z1_P0 : origin = 0x78420, length = 0x000010
/* B1 Z2 OTP. LinkPointers */
B1_DCSM_OTP_Z2_LINKPOINTER : origin = 0x78600, length = 0x00000C
/* DCSM B1 Z1 Zone Select Contents (!!Movable!!) */
/* B1 Z2 OTP. Flash partitioning */
B1_DCSM_ZSEL_Z2_P0 : origin = 0x78620, length = 0x000010
}
SECTIONS
{
b0_dcsm_otp_z1_linkpointer : > B0_DCSM_OTP_Z1_LINKPOINTER PAGE = 0, type = DSECT
b0_dcsm_otp_z1_gpreg : > B0_DCSM_OTP_Z1_GPREG PAGE = 0, type = DSECT
b0_dcsm_otp_z1_pswdlock : > B0_DCSM_OTP_Z1_PSWDLOCK PAGE = 0, type = DSECT
b0_dcsm_otp_z1_crclock : > B0_DCSM_OTP_Z1_CRCLOCK PAGE = 0, type = DSECT
b0_dcsm_otp_z1_bootctrl : > B0_DCSM_OTP_Z1_BOOTCTRL PAGE = 0, type = DSECT
b0_dcsm_zsel_z1 : > B0_DCSM_ZSEL_Z1_P0 PAGE = 0
b0_dcsm_otp_z2_linkpointer : > B0_DCSM_OTP_Z2_LINKPOINTER PAGE = 0, type = DSECT
b0_dcsm_otp_z2_gpreg : > B0_DCSM_OTP_Z2_GPREG PAGE = 0, type = DSECT
b0_dcsm_otp_z2_pswdlock : > B0_DCSM_OTP_Z2_PSWDLOCK PAGE = 0, type = DSECT
b0_dcsm_otp_z2_crclock : > B0_DCSM_OTP_Z2_CRCLOCK PAGE = 0, type = DSECT
b0_dcsm_otp_z2_bootctrl : > B0_DCSM_OTP_Z2_BOOTCTRL PAGE = 0, type = DSECT
b0_dcsm_zsel_z2 : > B0_DCSM_ZSEL_Z2_P0 PAGE = 0, type = DSECT
b1_dcsm_otp_z1_linkpointer : > B1_DCSM_OTP_Z1_LINKPOINTER PAGE = 0, type = DSECT
b1_dcsm_zsel_z1 : > B1_DCSM_ZSEL_Z1_P0 PAGE = 0, type = DSECT
b1_dcsm_otp_z2_linkpointer : > B1_DCSM_OTP_Z2_LINKPOINTER PAGE = 0, type = DSECT
b1_dcsm_zsel_z2 : > B1_DCSM_ZSEL_Z2_P0 PAGE = 0, type = DSECT
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
ASM:
;;############################################################################# ;; ;; FILE: f28004x_dcsm_z1otp.asm ;; ;; TITLE: Dual Code Security Module Zone 1 OTP ;; ;; DESCRIPTION: ;; ;; This file is used to specify Z1 DCSM OTP and zone select block ;; values to program. ;; ;; In addition, the 60 reserved values after the zone select block ;; are all programmed to 0x0000 as well. ;; ;; !!IMPORTANT!! The below memory sections are mapped to OTP (one-time ;; programmable) memory with the *dcsm_lnk.cmd linker command file. In order ;; to program the below memory sections, user should uncomment the .long words ;; of each section and change the value to what is desired. Additionally, the ;; corresponding section of *dcsm_lnk.cmd should no longer be labelled as a ;; dummy section. Remove ", type = DSECT" in SECTIONS from the memory section ;; that is being programmed. ;; ;; ;; !!IMPORTANT!! The "bx_dcsm_otp_z1_linkpointer" section contains the ;; Z1 LINKPOINTER which determines the location of the Z1 Zone Select block. ;; If the LINKPOINTER is changed, then the "bx_dcsm_zsel_z1_linkpointer" ;; section in the *_dcsm_lnk.cmd command linker file must also change to an ;; address decoded from the value specified in the Z1-LINKPOINTER location. ;; ;; ;; The "bx_dcsm_zsel_z1" section contains the actual Z1 Zone Select Block ;; values that will be linked and programmed into to the DCSM Z1 OTP Zone ;; Select block in OTP. ;; These values must be known in order to unlock the CSM module. ;; ;; It is recommended that all values be left as 0xFFFFFFFF during code ;; development. Values of 0xFFFFFFFF do not activate code security and dummy ;; reads of the Z1 DCSM PWL registers is all that is required to unlock the ;; CSM. When code development is complete, modify values to activate the ;; code security module. ;; ;; ******************************WARNING*************************************** ;; It is recommended not to program 0xFFFFFFFF to user OTP locations, if users ;; intend to comeback and re-program any of the bits to '0' in future. If user ;; programs 0xFFFFFFFF to any of the OTP locations then the ECC locations would ;; get programmed to a non erased state and users won't be able to comeback ;; and re-program the OTP location to another value. Please refer to DCSM ;; chapter of device TRM for more details on ECC for the locations in DCSM. ;; ;; Hence TI ships this example commenting out the initialization of all the ;; below locations. ;;############################################################################# ;; $TI Release: F28004x Support Library v1.07.00.00 $ ;; $Release Date: Sun Sep 29 07:29:19 CDT 2019 $ ;; $Copyright: ;// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ ;// ;// Redistribution and use in source and binary forms, with or without ;// modification, are permitted provided that the following conditions ;// are met: ;// ;// Redistributions of source code must retain the above copyright ;// notice, this list of conditions and the following disclaimer. ;// ;// Redistributions in binary form must reproduce the above copyright ;// notice, this list of conditions and the following disclaimer in the ;// documentation and/or other materials provided with the ;// distribution. ;// ;// Neither the name of Texas Instruments Incorporated nor the names of ;// its contributors may be used to endorse or promote products derived ;// from this software without specific prior written permission. ;// ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;// $ ;;############################################################################# .sect "b0_dcsm_otp_z1_linkpointer" ;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER1 ;; .long 0xFFFFFFFF ;Reserved ;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER2 ;; .long 0xFFFFFFFF ;Reserved ;; .long 0x1FFFFFFF ;B0_Z1OTP_LINKPOINTER3 ;; .long 0xFFFFFFFF ;Reserved .sect "b0_dcsm_otp_z1_gpreg" ;; ;; See the ROM Code and Peripheral Booting chapter of TRM for more details. ;; ;; Below is a description of the bit fields of Z1OTP_BOOTPIN_CONFIG ;; used by Boot ROM. ;; ;; | Key (31-24) | BMSP2 (23-16) | BMSP1 (15-8) | BMSP0 (7-0) | ;; ;; Below is a description of the bit fields of Z1OTP_GPREG2 used by ;; Boot ROM. ;; ;; | Key (31-24) | RSVD (23-8) | RSVD (7-6) | ESP (5-4) | RSVD (3-0) | ;; ;; .long 0xFFFFFFFF ;Z1OTP_BOOTPIN_CONFIG ;; .long 0xFFFFFFFF ;Z1OTP_GPREG2 .sect "b0_dcsm_otp_z1_pswdlock" ;; .long 0xFFFFFFFF ;Z1OTP_PSWDLOCK ;; .long 0xFFFFFFFF ;Reserved .sect "b0_dcsm_otp_z1_crclock" ;; .long 0xFFFFFFFF ;Z1OTP_CRCLOCK ;; .long 0xFFFFFFFF ;Reserved .sect "b0_dcsm_otp_z1_bootctrl" ;; ;; See the ROM Code and Peripheral Booting chapter of TRM for more details. ;; ;; Below is a description of the bit fields of Z1OTP_BOOTDEF_LOW used by ;; Boot ROM. ;; ;; | BOOT_DEF3(31-24) | BOOT_DEF2(23-16) | BOOT_DEF1(15-8) | BOOT_DEF0(7-0) | ;; ;; Below is a description of the bit fields of Z1OTP_BOOTDEF_HIGH ;; used by Boot ROM. ;; ;; | BOOT_DEF7(31-24) | BOOT_DEF6(23-16) | BOOT_DEF5(15-8) | BOOT_DEF4(7-0) | ;; ;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_LOW ;; .long 0xFFFFFFFF ;Z1OTP_BOOTDEF_HIGH .sect "b0_dcsm_zsel_z1" .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYRAM .long 0xFFFFFFFF ;B0_Z1OTP_EXEONLYSECT .long 0xFFFFFFFF ;B0_Z1OTP_GRABRAM .long 0x55555555 ;B0_Z1OTP_GRABSECT Select all Sector in Zone 1 .long 0x11223344 ;B0_Z1OTP_CSMPSWD0 (LSW of 128-bit password) .long 0x11223344 ;B0_Z1OTP_CSMPSWD1 .long 0x11223344 ;B0_Z1OTP_CSMPSWD2 .long 0x11223344 ;B0_Z1OTP_CSMPSWD3 (MSW of 128-bit password) .sect "b1_dcsm_otp_z1_linkpointer" ;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER1 ;; .long 0xFFFFFFFF ;Reserved ;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER2 ;; .long 0xFFFFFFFF ;Reserved ;; .long 0x1FFFFFFF ;B1_Z1OTP_LINKPOINTER3 ;; .long 0xFFFFFFFF ;Reserved .sect "b1_dcsm_zsel_z1" ;; .long 0xFFFFFFFF ;Reserved ;; .long 0xFFFFFFFF ;B1_Z1OTP_EXEONLYSECT ;; .long 0xFFFFFFFF ;Reserved ;; .long 0xFFFFFFFF ;B1_Z1OTP_GRABSECT ;; .long 0xFFFFFFFF ;Reserved ;; .long 0xFFFFFFFF ;Reserved ;; .long 0xFFFFFFFF ;Reserved ;; .long 0xFFFFFFFF ;Reserved ;;---------------------------------------------------------------------- ;; For code security operation,after development has completed, prior to ;; production, all other zone select block locations should be programmed ;; to 0x0000 for maximum security. ;; If the first zone select block at offset 0x10 is used, the section ;; "dcsm_rsvd_z1" can be used to program these locations to 0x0000. ;; This code is commented out for development. ;; .sect "dcsm_rsvd_z1" ;; .loop (1e0h) ;; .int 0x0000 ;; .endloop ;;############################################################################# ;; End of file ;;#############################################################################
Thanks
Sheldon
We are considering adding some optical isolation barrier for some new products. The Analog isolation chips available on the market do not provide
enough isolation for what we need.
As of now, the design options we have are:
1. PWM
2. ADC -> uController +DAC
3. MCU -MCU
The PWM option seems like a very good option due its lower cost and complexity. However, we are not sure about the performance. (linearity and bandwidth)
If we were to go one level higher in performance we were thinking of digitizing the signal and reconstructing after the isolation barrier. For that, however,
it seems like we'd have to decide if we''d go with a more granular approach involving ADCs or a more "off the shelf" option with MCUs.
We'd love to have >=1MSPS and 14 to 16 bits digitization. For reconstruction of the waveform, I'd hope to have the same sampling rate and similar resolution.
Could you please comment on the complexities involved in choosing one way or another? Would there be substantial savings either in terms of development time
and/or components depending on which route we'd select?
Hi there,
I'm designing a BMS based on yours TIDA-00792, which use the BQ78350DBTR-R1, BQ7694000DBTR and BQ76200PWR devices. My topology is a 14S1P.
I would like to add a secondary protection; I mean a chemical fuse (you know a fuse with a third leg capable to trigger its fuse via an internal heater).
I know that the device BQ7718 is designed just for this requirement; BUT BEFORE to add 3 of them on my design:
--> I would like to know if there are some way to add this feature with the BQ78350DBTR-R1 or BQ7694000DBTR. I'm trying to save this BQ7718 devices on my design.
Thanks a lot
Part Number: OPA858DSGEVM
Hi, an urgent help request.
We have purchased an Evaluation Module for OPA858 amplifier, OPA858DSGEVM several days ago, and have tried
the module to test it for our OPA858 pulse amplification circuit design for our product.
However, the module doens not work at all. we have found the circuit uses R3 zero ohm resistor connected
in parallel with the differential input terminal to the ground. That means resistor R3 shorts out the RF input signalm and
consequently the module doe not output any siganl waveform to eh oscilloscope at the output connector.
Why did you short the input terrminal by R3. How can we test the moduel? Please explain the situation. Is it an mistake?
Do we have to remove the resistor R3, which is also very small and thus even very difficult to remove it.
Please give me immediate answer. I don't understandwhy this happened.
Regards,
Ki-Chang Lee
P.S. My collegue Iksoo Choi already have asked this matter to you on Friday. But still he did not get answer from TI.
Part Number: TPS23754EVM-383
I built a board exactly as the TPS23754EVM-383, but the output is only 2.3V and unstable.
The VC voltage is around 11V, but the GATE and GAT2 are not driving the FETs( 0.2V on these).
Where do I need to look for diagnose , please !
Thank you very much,
Flaviu
Tool/software: Code Composer Studio
Hello All
I have some problem with developmnet and debugging application where the CM control USB Periphery.
I can not to see the registers of USB on the Cortex_M4_0 side. I can see this one only on the C28xx_CPU1 side.
Besause it is appiared only on the C28xx_CPU1 side, on the Cortex_M4_0 side it is absent.(For example CANA and CANB registers I can abserve on the both sides)
So statement HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD,
which is fulfilled on the Cortex_M4_0 side does not make any effect to the registers. Or at least I do not observe any changing on the C28xx_CPU1 side.
The Clock gating is configured on the both sides and PALLOCATE0 register configured to allocate USB_A to CM side.
Can somebody help me?
Information about Code Composer Studio
Version: 9.1.0.00010
OS: Linux, v.5.0.0-32-generic, x86_64 / gtk 2.24.32
Java version: 1.8.0_112
Best regards
Andrii
Part Number: MSP430F5529
Hello,
I am trying to implement a millisecond counter that can operate for 24 hours without overflow. The purpose is to create time stamps for event log with distinguishable milliseconds. No external clock source available.
RTC in 32-bit counter mode seems to be the only option, but I couldn't find any examples on how to set it up. Can you please share some or suggesto some other way to solve the problem?
Regards,
Konstantin
Part Number: TPS61202
Hi,
My customer requires TI to provide the Isw of average switch current limit at Vout=5V. I refered Figure.1, but it's shows output current ability. What is the exact value of the current limit at Vout=5V?
Best Regards, Taki