Part Number: DP83867IR
Hello everybody,
my customer designed with DP83867IS/CS before, now he finally wants to use DP83867IR.
Is there anything he needs to consider in his schematics and layout comparing to the SGMII version?
Is there maybe a roll over documentation?
Kind regards,
Marion
Part Number: LP87702-Q1
when LP87702 input is 5V，the two bucks have no output，why？
LP87702：VANA=VIN1=VIN2=EN1=NRST=5V。
but VANA=VIN1=VIN2=EN1=NRST=4.2V，the two bucks can work。
Part Number: PROCESSOR-SDK-AM65X
Dear TI team,
I've been investigating an issue with our own application that looks very similar to another issue posted before (https://e2e.ti.com/support/processors/f/791/t/787929), but that thread unfortunately ended without a solution since the problem "disappeared".
The symptoms are very similar to what the original post describes: Our application has a thread that repeatedly calls Task_sleep(1), and eventually that thread "dies" because according to ROV the timeout is 4 billion + (actually a small negative number). In our case there are also two interrupts involved, the timer interrupt and a PRU interrupt (from the ethercat slave firmware).
What happens is that the timer interrupt is triggered, and the interrupt processing gets within ti_sysbios_knl_Clock_doTick__I() up to the point where (&ti_sysbios_knl_Clock_Module__state__V)->ticks++ has been incremented but ->swiCount++ not yet. At this point the timer interrupt is preempted by a PRU interrupt which runs until completion. At that moment a NEW timer interrupt is being processed, i.e. the core is not resuming processing of the original timer interrupt, but starts executing from ti_sysbios_family_arm_v7r_keystone3_Hwi_dispatchIRQ__I(). That interrupt processing also moves through ti_sysbios_knl_Clock_doTick__I(), increments ->ticks++ once more, and then triggers the clock SWI. At that point ->ticks has been incremented twice, but ->swi_count was only incremented once, causing the timeout for our Task_sleep(1) to be missed. If I manually "correct" the corresponding Clock object's ->currTimeout processing resumes just fine.
The real issue is apparently that the timer interrupt is preempted by the PRU interrupt but then doesn't get to finish processing, but rather takes the timer interrupt again.
The VIM chapter in the TRM (revision D) has a small paragraph on interrupt priorization that seems to suggest that the VIM would keep track of preempted interrupts:
If the CPU switches this interrupt to active (by reading the
VIM_FIQVEC/VIM_IRQVEC register), then the currently active interrupt will be pushed onto a stack. When
an interrupt is cleared by reading the VIM_FIQVEC/VIM_IRQVEC register, if there are any interrupts on
the stack, the first entry is popped off and put back into the VIM_ACTFIQ/VIM_ACTIRQ register, so that
software may continue where it left off.
Unfortunately the TRM is otherwise rather sparse on the details of this "stack", e.g. it doesn't say anywhere how deep that stack is.
I'm currently using SYS-BIOS from 6.75.02 from processor SDK 06.00, but I also gave SYS-BIOS 6.76.02 (latest download on the website) a try, unfortunately with the same results.
Regards,
Dominic
Part Number: AWR1642BOOST
I can properly run od_demo.exe (with 2 zones), but I want to change the sensitivity of the zones, since they light up red to easily for my purpose.
Does anyone know how to change this in the MATLAB code?
Part Number: SN74LV4T125
Is it acceptable to connect the thermal pad for the RGY package variant of SN74LV4T125 to GND?
It doesn't state in the datasheet what this pin internally connects to, and whether or not it is allowed to be connected to anything. By default I would assume therefore we must leave it unconnected, however in a current design it would make routing considerably easier if it is acceptable to connect to GND.
Part Number: TMP102EVM
Hi Sir,
the following picture is our use the TMP102EVM read All Reg function got waveform,
What is Area A Representative meaning?
Hugo
Part Number: TMS320F28027F
I'm applying a Step of the maximun speed to see the response.
I tried change the USER_MOTOR_MAX_CURRENT but this not solved it.
I tried change The speed PID , acceleration and the current increases a little bit.
In the first tests I saw 30A in the rail and changing the speed PI I saw 35-37 in the rail. I want the double!!!!
Increasing USER_MOTOR_MAX_CURRENT I didn't saw any changes, until I increase like 3x the motor got unstable.
I'm working on lab05.
Part Number: LM5114
Hi Team,
My customer is building PCBA 3D file then he found LM5114's step file is not match outline drawing shown in datasheet. Could team help support this case.
Thanks a lot.
VIncent Chen
Part Number: 66AK2G12
Tool/software: Code Composer Studio
Dear Rahul,
Currently, We develop our product using 66AK2G12,
And debug the DSP and ARM via Jtag using CCS.But there are some issues. Please advice.
We made the following changes from EVM to DDR3.
・The chip changed from 4(+1 for ECC) to 1 piece.
・The data width changed from 8-bits to 16-bits.
So we set the NM of EMIF_SDCFG Register to DDR3 data bus width is the 2 = 16-bit bus width.
Are there any other register need to change for DDR3 bus width change?
(Are there any register need to change about MSMC registers and other registers?)
Best regards.
Part Number: LAUNCHXL-F28379D
Tool/software: Code Composer Studio
Hello,
I'm currently trying to configure a PWM for a 3-phase inverter with adjustable high resolution frequency (arround 1MHz), dead time and a fixed duty cycle of 50%.
My first idea was to use both HR period and HR phase shift to obtain an accurate frequency with the +/-120° phase shift that is mandatory for the application but it looks like those 2 modes are not compatible. So instead I'm using the CMP/CMPHR registers.
My first attempts were with a 200MHz systclock but apparently the intOsc2 should not be used beyond 194MHz so I have been using a 100MHz frequency with a /1 EPWMCLKDIV which worked for the normal PWM but not for the HR (apparently there is an issue when the CLKDIV is not set to /2). So now my system is configured with a 180MHz SYSCLK and a 90MHz PWMCLK/TBCLK (so 1 TBCLK is 11ns).
Nonetheless I am not able to sychronise EPWM1/EPWM2 and EPWM3. EPWM1 and 2 are perfectly aligned but there is a 3.2ns delay for EPWM3 (I can't figure from where it comes as few MEP should be less than that and 1 TBCLK is more). I followed the technical manual p1967 (15.14.1.5.4.1) which said:
I don't really understand if this is mandatory when the Phase shifting module is not used. Anyway, It doesn't change anything on my sync problem (I reconfigure the input5 xbar so that PWM1 doesn't send to much synch pulse). Also, should we send the software sync pulse before or after reenabling TBCLK ? In my opinion we should send the pulse before so that all the PWM are synchronised without possibilities of propagation latency.
So as long as It appears I can't use the phase shift synchronisation tactic, I believe that the software sync pulse would not be usefull. My only remaining strategie is to force the counters to 0 and then start the clocks and hope the PWM will always remain synchronised even when I change the period ? Furthermore It is written that the software pulse would introduce jitter. But the 3,2ns lag remains...
Here is my configuration:
And this function is used to define the CMP register (for the example the phase shift is set to 0, all the PWM should be the same)
The tricky part is to obtain the Q16 format for the CMPHR with up and down count (I find the explanations in the technical reference manual not very clear on this question).
Thank you for your help
Benjamin LOYER
Part Number: TLV757P
Hi TI Team,
We are using TLV757P component in our design,
Please find the attached schematic and review the same and share your valuable comments on this to improve the design.
Thanks
Manjunath.
Hello,
for an upcoming project of a portable device that has the possibility to be connected to an USB 2.0 host system I want to implement a power supply OR-ing scheme where I actively switch from my primary battery supply (possibly alkaline primary battery) to the supplied 5V from the USB VBus if it is available to safe battery life time. I first thought of switching between the two supplies with my used microcontroller if VBus is sensed but after some research I found the SLVAE57 application report from TI and thought your ideal diode controllers might be a solution also integrating battery protection for reverse currents or wrong polarity battery insertion.
I searched in your product tree but I am not sure if this is the right solution for my project.
These are my powers supply requirements so far:
As the TPS6300 can operate from 1.9V - 5.5V I would only need a suitable OR-ing scheme chip with integrated battery protection.
I would be happy if someone could give me some suggestions.
best regards
Benjamin
Part Number: TIDA-01093
Dear all,
Please provide Balance time and Balance current for TIDA-01093.
Waiting for earliest reply.
Thanks and regard,
Prathamesh Patil
Part Number: TPS23881
The attachment is a circuit diagram drawn by my client. He wants to use 1 port , 4-pair mode. I would like to ask:
Need to use Q504, Q505 two sets of Mosfet?
Does U1's PIN48~51 need to be connected?
Is the PIN44, 45, 53, 54, 55, 56 of U1 connected to the firmware side?
Part Number: CC2642R
1. SDK simplelink_cc13x2_26x2_sdk_3_30_00_03
2. CCS 9.2
======================
1. I imported project bim from C:\ti\simplelink_cc13x2_26x2_sdk_3_30_00_03\examples\nortos\CC26X2R1_LAUNCHXL\bim\bim_onchip
I created a file "my_ccfg.c" and link it to folder "Application". Bellow is content of file "my_ccfg.c"
#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x56000
#include <ti/devices/DeviceFamily.h>
//#####################################
// Bootloader settings
//#####################################
#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE
// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader
#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader
#endif
#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL
#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor
// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor
#endif
#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER
#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0x19 // DIO number for boot loader backdoor
#endif
#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE
#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor
//#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor
#endif
#include DeviceFamily_constructPath(startup_files/ccfg.c)
2. I imported project C:\ti\simplelink_cc13x2_26x2_sdk_3_30_00_03\examples\rtos\CC26X2R1_LAUNCHXL\ble5stack\project_zero
3. I compiled both projects and download multiple images into my board ( NOT LAUNCHXL-CC26X2R1) by smart flash 2
BUT, the project zero doesn't work. I can not search ble "project zero"
I imported simple_peripheral and compiled and download it, it work well.
While simple_peripheral_oad_on(off)chip doesn't work.
Part Number: TPS65988
Hi team,
Is it possible to know why the I2C rising time when PD is configured as I2C master does not specify in the datasheet? Thanks!
Best Regards,
Leroy Song
Part Number: 66AK2G12
Tool/software: Code Composer Studio
Dear Rahul,
Currently, we are developing products using 66AK2G12.
Debug DSP and ARM via Jtag using CCS, but there are some issues. Please let us know what you think.
The problems are as follows.
When the main program starts from DDR3 (using Jtag), we can write correct value to DDR3.
When the main program is started from other (cache or shared memory),
we can write to DDR3, but the value is not correct value.
we asked to below URL. Are there related?
e2e.ti.com/.../848220
Best regards
Part Number: BQ24076
I had similar issue which is not solved and meanwhile my client abandoned the project as his private issue. No I have new design, nee to power cellular modem powered 5-6V@1A solar panel outdoor use, during testing from PC USB connector. The battery is LiPO type or in some cases LPK, single cell 12000 mAh capacity. I always facing issues using TI chargers, need to learn better the subject. Now I limited in time and in BQ24076 data sheet offered few other part numbers which I don't know which one to select for best performance. I need urgent solution and deliver the project. The client willing to start to manufacturing ASAP.
BQ24076 section of the circuit delays the deliver the project. I want to upload the schematic, but I don't see option to upload files here.
Part Number: MSP432P4111
Tool/software: Code Composer Studio
What are the probabilities of occurring I2C start interrupt (EUSCI_B_I2C_START_INTERRUPT) in the MSP432P4111 device?
Does I2C start interrupt (EUSCI_B_I2C_START_INTERRUPT) in MSP432P4111 work with EUSCI_B_I2C in Master transmitter configuration?
Part Number: MSP432E401Y
Tool/software: Code Composer Studio
Hi,
I'm considering ADC of MSP432E401Y.
I use CCS9.2, Smplelink3.30.00.22 and MSP-EXP432E401Y.
I'm correcting a sample program and am reading the adc value of AIN17 (PK1).
ADCbuf was taken up here before, so it was confirmed to be corrected.
However, I select AIN17 (PK1) in Adcbufcontinuous sample, it can't read the true value.
I used below for a sample of ADCbuf.
\ti\simplelink_msp432e4_sdk_3_30_00_22\examples\rtos\MSP_EXP432E401Y\drivers\adcbufcontinuous\tirtos\ccs
And I used below for a sample of ADC.
\ti\simplelink_msp432e4_sdk_3_30_00_22\examples\rtos\MSP_EXP432E401Y\drivers\adcsinglechannel\tirtos\ccs
Advice, please.
Thanks