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TDA4VMXEVM: TDA4VM SOM fabrication issues and questions

September 20, 2019, 11:44 am
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Part Number: TDA4VMXEVM

We have prepared the TDA4 SOM for manufacturing using the TI recommended stackup, material and trace/space requirements, essentially reproducing exactly the physical nature of the design. We have engaged a fabrication partner and submitted a preliminary fabrication package for a DFM analysis of the design. The results of that DFM analysis indicate 2 major issues:

  1. Inability to achieve the minimum trace/space requirements of 3 mils when specifying 1oz. Cu. The fabrication partner is recommending 4 mil trace/space @ 1oz. Most of the spacing issues appear to be correctable, which we can take care of.
  2. Inability to achieve impedance requirements of 66 ohm single-ended and 132 ohm differential on L3. the fabrication partner is able to achieve ~56 ohm /111 ohm on L3.

 

Questions:

  1. Do you have a more detailed stackup (from fab house) we can reference to see how you were able to manufacture this design? This would be extremely helpful to us because we won’t have initiate major changes to routing, etc.
  2. Does TI recommend maintaining 1 oz. Cu. on all inner signal/power layers? If so, we will need to increase width on all 3 mil wide stripline routing, affecting various high-speed interfaces, including DDR CA/CLK. Furthermore, can DDR impedance be reduced from 66/132 if necessary? Are the exact impedance critical, or just the impedance relationships between the DDR branches (33/66/132 ohms)?
  3. Alternatively, would ½ oz Cu. be acceptable on inner signal layers (L3, L5, L7, L10, L12, L14), while maintaining 1 oz planes? We’re concerned this may affect power integrity as many power pours exist on these layers.

 

The fabrication partner reference stackup is attached.

(Please visit the site to view this file)

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DCA1000EVM: Port numbers

September 20, 2019, 11:50 am
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Part Number: DCA1000EVM

I am trying to set up u the DCA1000 for raw data capture from  the AWR1642, however when I downloaded mmWave Studio the  FDI CDM  Driver package installation  failed with a warning; "Unable to install FTDI drivers , unknown signal". 

I connect the DCA to my computer  and per instructions in the User Guide tried to search  for  drivers but was unsuccessful. How do I get the port numbers for tis device?

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ADC141S628-Q1: adc141S628-Q1

September 20, 2019, 11:55 am
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Part Number: ADC141S628-Q1

I would like to understand the difference between total unadjusted error(TUE) and effective number of bits (ENOB).  I am doing a worst case analysis from -40c to 105c and need to know if I should use TUE values or ENOB values to evaluate the true number of bits that this A/D will provide.

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CCS/TM4C1290NCPDT: Halting at input GPIO ISR how to look at stack

September 20, 2019, 11:55 am
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Part Number: TM4C1290NCPDT

Tool/software: Code Composer Studio

I am debugging an application reset issue. I have an external processor monitoring the application

watchdog toggle pulse that will trigger a falling edge interrupt when it runs into trouble. While I can

halt when this ISR triggers, how do I go about looking at past instructions/functions that the applicaiton

was executing?

Thanks,

Priya

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LM4040-N-Q1: AEC Qualified?

September 20, 2019, 11:56 am
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Part Number: LM4040-N-Q1

Hello - My understanding of the datasheet for the LM4040 is that the AEC qualified parts are LM4040Q+suffix.  This seems to line up with the TI website which claims that the LM4040 is auto qualified for 2.5V and 3V parts.  Can I assume all Q+suffix LM4040 devices are AEC qualified?  Thank you.

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MSP430FR2522: Critical very long uptime

September 20, 2019, 11:57 am
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Part Number: MSP430FR2522

Hello,

I need to design a system that needs to run for several years non stop. It is critical that it wakes up about once a minute (exact time is irrelevant, just the interval in itself needs to be constant) for this entire period.

So I have two problems I that I still need to think about. 

First are the firmware updates. It is ok to update the firmware in between the intervals. The current data is stored in external FRam so the processor can be reset and return to the last state. It just may not interrupt the task it does every minute. Any tips on how to do this "the good way"? I thought of putting the firmware in an external flash first an then have the MSP update itself when the task is done. Or using a custom serial bootloader that simply only answers when it has just finished the task, thus giving about a minute to update. The timeinterval is given by an external little timer that already puts out a ~1 minute pulse, so it will not fall out of sync after updating. 

The second issue is the power. I have planed a BQ2407x that would usually run from a USB mains adapter and functions as UPS with a Li Lion battery. But I need to have a sort of emergency backup CR2032 on the same PCB that would come into action if all other sources from the BQ fail. How could I do this? The application is very low power (idle 15µA, active 20mA for a very short time), so a CR2032 should last for enough time to get the main supply running again. Any tips or devices that can do that?

Thank you

Kind regards

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CCS/MSP432P401R: How can I program BMI160 using MSP432P401R?

September 20, 2019, 12:05 pm
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Part Number: MSP432P401R

Tool/software: Code Composer Studio

Hi TI community

I plan to program BMI160 sensor for motion feedback in my application with MSP432P401R. Does anyone have a guide or reference to help me with?

I appreciate it!

Saber 

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TPS7A92: TINA Simulation of NRSS pin Voltage

September 20, 2019, 12:05 pm
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Part Number: TPS7A92

Hello,

I've been trying to simulate of model of TPS7A92 in TINA, and I noticed something unusual. I've attached my simulation to this (a .jpeg and a .tsc, although I'm not sure if the attachment tool supports.tsc), and there are two cases: my design (upper) and the typical application in the TI datasheet (lower).

The simulation indicates that the voltage across the capacitor connected to the NRSS pin (VF3/VF6) perpetually increases. I think that's a bit odd, so I was wondering if you could suggest any strategies for checking my simulation setup. 

(Please visit the site to view this file)

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[FAQ] UCC23513: NEW White Paper: How Capacitive Isolation Solves Key Challenges in AC Motor Drives

September 20, 2019, 12:07 pm
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Part Number: UCC23513

My colleagues have just published a White Paper, titled, "How Capacitive Isolation Solves Key Challenges in AC Motor Drives." You can find it here: 

Signal and power isolation help ensure reliable operation of AC motor drive systems and protect human operators from high voltages. Not all isolation technologies are created equal, however, especially in terms of device lifetime and temperature performance. This white paper compares Texas Instruments’ (TI) capacitive-based isolation technology with traditional isolation technology when solving alternating current (AC) motor design challenges, including isolating gate drivers in the power stage, isolating voltage or current feedback, or isolating digital inputs in the control module.

For further information on gate drivers, please see ti.com/gatedrivers

If you need assistance with the UCC23513, please post a request on e2e.

Thank you.

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LM22676: Output Power Applied, Input Unpowered

September 20, 2019, 12:12 pm
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Part Number: LM22676

What, if any, are the consequences of applying an output voltage sourced from another power supply with the input unpowered but connected to various components. This is an adjustable version set to 5.25V.

In the unusual condition:

The Vo = 5.218V. We lifted pin 8 and measured 14.0 mA into pin 8.

We measured Vfb (pin pin 4) to be 0.0V. The current into pin 4 was 1.69mA.

We lifted pin 7 (Vin) and measured the current out of pin 7 to be 11.22 mA and the Vin = 4.66V

After the unusual condition, there appears to be no damage and the supply still functions normally when powered properly from Vin.

Regards,

Larry

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TPS81256: Operation at 90C Ambient Temp

September 20, 2019, 12:24 pm
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Part Number: TPS81256

Hi,

My customer is planning to use the TPS81256 for a 3.3V to 5V @ 440mA Ioutmax application. The device will be sealed in an enclosure with no airflow so there is a chance the Ta will increase beyond 85C (they estimate up to ~90C). Do you see any issues with this? I see that the datasheet recommends a Tj of 110C for max power operation, and with very rough calculations it seems like they will be right around that junction temp at max power and 90C Ta. They are also operating well below the max switch current of the device.

Please let me know your thoughts. It would be great if there is any derating data for Tj higher than 110C.

Thanks,

Antonio

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CCS/TMS320F28379D: PID Controller

September 20, 2019, 12:33 pm
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Part Number: TMS320F28379D

Tool/software: Code Composer Studio

Hi,

I am directly trying to use F28069_PID example project  in DCL folder in ("C:\ti\c2000\C2000Ware_2_00_00_02\libraries\control\DCL\c28\examples\F28069_PID"). I know the headers are different in submodules but how can I fix it? Here is what I did after importing the project:

1)I used (Link File to Project) to link my target configuration.

The project Builds. After hitting Debug, when I am trying to run it, in the first try nothing happens. The  Debug window shows           0x3FE493 (no symbols are defined). If I hit the Resume button again, I show running. And at the same time shows: Break at address "0x3fe493" with no debug information available, or outside of program code.

Disassembly page : 3fe493:   7625        ESTOP0 

I appreciate if there is any help. I don't feed any input and not connecting any jumper wires. I was just trying to run the project first.     

Also, to check the output results I need to check "ADCRESULT0" in Memory Browser page. Right?

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SN74LVC8T245: Output stage question

September 20, 2019, 12:41 pm
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Part Number: SN74LVC8T245

For the SN74LVC8T245, the the B-Port outputs allow for the following use case?

The aim is to reverse bias the diode when A-port input is high.

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TPS53915: Power Loss in Controller

September 20, 2019, 12:42 pm
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Part Number: TPS53915

Hello,

I am looking to calculate the power loss inside this controller. What is the best way to go about doing that?

-Michael

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TPS24720: TPS24720RG meaning of G

September 20, 2019, 12:43 pm
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Part Number: TPS24720

Hello,

What does the G stand for in this part number ? TPS24720RGTR ?

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SN65MLVD200A: Why do I see 6ns end to end delay on differential MLVDS signals with 10.5ft of 100 ohm twisted pair and 19 transceivers?

September 20, 2019, 12:36 pm
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Part Number: SN65MLVD200A

I have a multi-drop M-LVDS network prototyped with 4-layer boards with a clock transceiver and a data transceiver for each of 19 nodes. The transmission line is CAT 5e with 100 ohm terminations at each end. The length of twisted-pair wiring is approximately 7" between nodes. The two nodes at each end of the network are attached to microcontrollers, for at total of four microcontroller. Each microcontroller has a SPI-master only driver that connects to the transmitter MLVDS ICs one each for clock and data, and each microcontroller has a SPI-slave only receiver that is connected to the MLVDS receiver. With a clock of 80MHz (12.5ns bit time) I am seeing a longer delay for the data than the clock, 6ns on the differential side and an additional 2ns from single-ended transmit signal to received single-ended signal when compared to the clock. The difference in length between the twisted pairs due to different twists per foot (21 vs 32) doesn't account for the 6ns delay as its only ==. I expect to see similar delays on clock and data signals. The result is a large number of CRC errors due to the data shifting a bit time. Do you have any ideas why this is happening and how to prevent it?

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LM2734: switch current limit (protection) vs actual output load current

September 20, 2019, 12:56 pm
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Part Number: LM2734

Hi,
I'm analyzing a good working LM2734X circuit. I'm looking for advice on how to use the data given in the data sheet to predict the behavior when a fault happens that triggers the internal protection system. I'm also interested in the behavior when a fault condition is just below the threshold of the internal protection system.
My aim is to determine the maximum input current and output current that can flow in the case of a circuit fault. The kind of circuit faults I have in mind are things such as a short circuit or a near-short circuit in the load, or in the inductor or capacitor(s) at the voltage regulator output.
The LM2734 data sheet (rev K) description says it can drive 1 ampere loads (text in sections 1 and 3). Nowhere in the specifications (section 6) is a max Iout given. The "switch current limit" Icl is given as 1.2A to 2.5A, with 1.7A typical under certain conditions. This switch current is that of the internal NMOS switch.
Since I can control the load current through varying the load, but I cannot directly control the switch current, I figure I need to increase the load current to increase the internal switch current. When the switch current reaches the current limit threshold (somewhere in the 1.2A to 2.5A range) the output will be disabled. From that, I will know the load current that led to the current limit shutdown, but I still won't know the corresponding switch current value.
Question 1: Is there a better way to determine the internal switch current limit under my operating conditions?
Question 2: Can we predict the current limit given our specific operating conditions? (Figures 3 and 4 in the data sheet don't match my operating conditions)
Question 3: Is there a calculation or approximation for internal switch current given the load current?
Regards
Carl
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TPS3824: How sensitive is TPS3824 to WDI transitions while asserting nRESET?

September 20, 2019, 1:02 pm
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Part Number: TPS3824

The TPS3824 PMIC includes a watchdog capability which will assert its nRESET signal if its WDI input has not been toggled recently.  (In addition to asserting nRESET if the voltage supply being monitored is too low.)

This capability also includes a feature wherein if the WDI input is toggled while the TPS3824 is currently asserting nRESET then the TPS3824 enters a state wherein nRESET is latched, that is it is continuously asserted until the power to the TPS3824 is cycled, regardless of the state of watchdog servicing during WDI.

This feature represents a risk to our product.  If nRESET is latched, our product cannot function!  I appreciate that this risk can be ameliorated by using a FET to decouple WDI while nRESET is asserted; furthermore that replacing our TPS3824 with a TPS3823A could remove this risk entirely.  We are considering these options.  Right now, however, I would like to make sure we have this risk well characterized, in order to have a good understanding of our exposure.

How sensitive is the WDI logic while nRESET is asserted?  I assume that it cannot be as simple as "any H->L or L->H transitions on the WDI inputs while nRESET is asserted will cause nRESET to latch."  After all, the act of asserting nRESET itself has a reasonable chance of _causing_ a transition on the WDI input, given the range of circuitry the TPS3824 might be connected to.  Indeed, even if we use a FET to gate our WDI input, the act of switching WDI from being actively-driven to being high-impedance could conceivably be interpreted by the TPS3824 as a WDI transition.

As such, I have to believe that there's a bit of complexity there.  Perhaps the TPS3824 needs to see more than one WDI transition before it latches.  Perhaps it includes a time delay, where any WDI transitions that happen "soon" after nRESET is asserted are ignored.  Perhaps there is some other kind of filtering involved.

Providing more detail as to how this latching feature works would be of tremendous help in characterizing our risk.

--thx

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TMS570LS3137: Using RTI event0 to HW trigger MibADC1 Group2 conversion

September 20, 2019, 1:02 pm
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Part Number: TMS570LS3137

Hello there,

In our project we are using RTI compare block 0 as HW source to trig the MibADC1 Group2 conversion every 50 ms, and everything is going fine when the associated RTI compare block 0 interrupt is enabled, within which ISR the ONLY instruction "RTIINTFLAG &= 0x00000001;" is used to reset the event0 interrupt flag in order to prepare for the next one in 50ms. This cycle repeats continuously, which confirms that the RTI was correctly programmed and the MibADC1 Group2 is converting every time.

However, if the interrupt generation from the RTI compare block 0 was disabled (by clearing the SETINT0 bit of the RTISETINTENA register), because we don't need this SW interrupt overhead, and thinking that the internal HW trigger would continue to trig the MibADC1 Group2 conversion. But it doesn't because no more conversion are performed.

Our question is: how to NOT generate RTI compare block 0 interrupt while keeping the cyclic HW trigger active every 50 ms?

Many thanks,

Chuck.

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SN74CBTLV1G125: question on the DATASHEET

September 20, 2019, 1:03 pm
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Part Number: SN74CBTLV1G125

Hi,

I have a question regarding this part,

The datasheet specifies a VinHighMin of 2V when supplied at 3V3.

We assume the A to B connection are 2 FET switches so it should not care about high or low as it is just an analogue connection. The VIN levels should only be applicable on the OEn input, but the datasheet is not clear on that.

Are these assumptions correct and can we connect an LVCMOS18 signal to the A-port of the device?

The device will be supplied by 3V3, OEn will be tied to GND.

Thanks and regards.

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