Part Number: UCC256302

Tool/software: WEBENCH® Design Tools

Hi,

I'm designing LLC converter with UCC256302 on webench. Is it possible to creating a custom mosfet like passive components?

Best regards,

Ali AYKAN

Part Number: BQ30Z554-R1

Hi support team!

 We need to update the chemistry on several batteries with bq30z55_v1.05 build 0.19 as Gas Gauge. And found bqEVSW does not have configuration profile for this IC.

Can you please provide us with bq30z55_1_05.encr to complete the task.

Thanks in advanse and best regards!

Part Number: PROCESSOR-SDK-AM335X

Tool/software: TI C/C++ Compiler

Im trying to config the dts of kernel 4.19 for a upgrade of 3.2. The ethernet transceiver are double lan8710.

Now the eth0 is working well but eth1 could only transmit but not receive.

I use wireshark for the test. As i ping my pc, I got the arp packet from eth1 and my pc return the mac address for arp, but eth1 would not reply any other packet.

The same test to eth0 has no problem.

The ifconfig  command  shows no rx packets from eth1:

root@am335x-evm:~# ifconfig
eth0 Link encap:Ethernet HWaddr 7C:38:66:FB:47:41
inet addr:192.168.3.11 Bcast:192.168.3.255 Mask:255.255.255.0
inet6 addr: fe80::7e38:66ff:fefb:4741/64 Scope:Link
UP BROADCAST MULTICAST MTU:1500 Metric:1
RX packets:129 errors:0 dropped:0 overruns:0 frame:0
TX packets:12 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:13962 (13.6 KiB) TX bytes:986 (986.0 B)
Interrupt:40

eth1 Link encap:Ethernet HWaddr 7C:38:66:FB:47:43
inet addr:192.168.4.11 Bcast:192.168.4.255 Mask:255.255.255.0
inet6 addr: fe80::7e38:66ff:fefb:4743/64 Scope:Link
UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:384 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:24744 (24.1 KiB)

lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
inet6 addr: ::1/128 Scope:Host
UP LOOPBACK RUNNING MTU:65536 Metric:1
RX packets:1689 errors:0 dropped:0 overruns:0 frame:0
TX packets:1689 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:120136 (117.3 KiB) TX bytes:120136 (117.3 KiB)

I checked the register in uboot by mii command, found nothing wrong.

My dts is as fllowing:

cpsw_default: cpsw_default {
pinctrl-single,pins = <

/* Slave 1 */
AM33XX_IOPAD(0x90c, PIN_INPUT_PULLUP | MUX_MODE1) /* (H17) gmii1_crs.rmii1_crs_dv */
AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* (J15) gmii1_rxer.rmii1_rxer */
AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (J16) gmii1_txen.rmii1_txen */
AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* (K17) gmii1_txd0.rmii1_txd0 */
AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* (K16) gmii1_txd1.rmii1_txd1 */
AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* (M16) gmii1_rxd0.rmii1_rxd0 */
AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* (L15) gmii1_rxd1.rmii1_rxd1 */
AM33XX_IOPAD(0x944, PIN_INPUT | MUX_MODE0) /* (H18) rmii1_refclk.rmii1_refclk */
/* Slave 2 */
AM33XX_IOPAD(0x864, PIN_INPUT_PULLUP | MUX_MODE3) /* (U16) gpmc_a9.rmii2_crs_dv */
AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE3) /* (U17) gpmc_wpn.rmii2_rxer */
AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (R13) gpmc_a0.rmii2_txen */
AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE3) /* (V15) gpmc_a5.rmii2_txd0 */
AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE3) /* (R14) gpmc_a4.rmii2_txd1 */
AM33XX_IOPAD(0x86c, PIN_INPUT_PULLUP | MUX_MODE3) /* (V17) gpmc_a11.rmii2_rxd0 */
AM33XX_IOPAD(0x868, PIN_INPUT_PULLUP | MUX_MODE3) /* (T16) gpmc_a10.rmii2_rxd1 */
AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE1) /* (H16) gmii1_col.rmii2_refclk */
>;
};

&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
dual_emac;
status = "okay";
};

&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};

&cpsw_emac0 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "rmii";
dual_emac_res_vlan = <2>;
};

&phy_sel {
rmii-clock-ext;
};

I have no more idea about it, and i have changed  pin PULLUP or DOWN as lan8710's  datasheet. But it seems no affection.

What could do more for the problem?

Part Number: IWR1443BOOST

My device is IWR1443 in 4Rx+3Tx mode. Does it theoretically create four antennas data after 1st Dimension FFT?

If so, from the visuallizer figure, which antenna does the demo visualizer recieve and display the range profile data? Or are they the same ?

Part Number: TAS2505-Q1

Hi there,

I have some question on the TAS2505-Q1 before starting the layout: 

1. Is the Reset Input in the IOVDD (3V3) Power Domain?
2. What do you recommend with non-used pins? In our case SPI Interface, I²S Interface and HPOUT.

Can you also let me kno the answer to the question below about the parallel routing for the two analog Inputs (Pin3 and Pin4) :

1. What is the recommended Impedance between both tracks?
2. Is there a Recommendation about the Distance between these tracks?
3. Are there any demands for length alignment for the two analog tracks?

Thanks and best regards,

Oz

Part Number: TMS570LC4357

Hi,

I am trying to implement DMA based receive of a block of CAN data, I have configured DCAN 1 for CAN transfer(which is working fine for functionalities other than DMA) and using DCAN 1 IF3 for receiving data by DMA.
I have configured 8 mailboxes for the same and transmitting 8 can frames by Microchip CAN BUS analyser transmit features.

Below is my code for DMA with CAN- 

uint32 RX_DATA1[D_SIZE]= {0};    /* receive  buffer in sys ram */
uint32 DMA_Comp_Flag;
g_dmaCTRL g_dmaCTRLPKT;    /* dma control packet configuration stack */
main()
{
 
//can initialization functions 
 
 // IF3 configuration for DMA
    //Enable DE3 bit in CTL register to trigger DMA when IF3 receives data
      canREG1->CTL |= (1U << 20U);

      // Read DATA A & B - 8 bytes */
      canREG1->IF3OBS = 0x18;

      // Message box 9-16 configured for auto update
     canREG1->IF3UEy[0]= 0x0000FF00;
  

      /* - DMA Configuration */
      /* Enable DMA */
      dmaEnable();

      /* Enable Interrupt after reception of data */
      dmaEnableInterrupt(DMA_CH0, FTC, DMA_INTA);

      /* assigning dma request: channel-0 with request line - 16 ( DCAN1IF3) */
     dmaReqAssign(DMA_CH0,16);

 /* Reset the Flag */
 DMA_Comp_Flag   = 0xAAAA5555;

                                                 
  while(1)
  {

    dmaConfigCtrlRxPacket((uint32)(&(canREG1->IF3DATx[0])),
           (uint32)(&RX_DATA1),
            2); //element count

    /* - setting dma control packets for transmit */
    dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);

              // dmaEnable();
    /* - setting the dma channel to trigger on s/w request */
    dmaSetChEnable(DMA_CH0, DMA_SW);

    /* Wait for the DMA interrupt ISR to set the Flag */
    while(DMA_Comp_Flag != 0x5555AAAA);

   /* Check the RX_DATA1 for the received message */
   asm(" B $");

  }
 
  where :
  void dmaConfigCtrlRxPacket(uint32 sadd,uint32 dadd,uint32 dsize)
{
    g_dmaCTRLPKT.SADD      = sadd;              /* source address             */
    g_dmaCTRLPKT.DADD      = dadd;              /* destination  address       */
    g_dmaCTRLPKT.CHCTRL    = 1;                 /* channel control +1          */
    g_dmaCTRLPKT.FRCNT     = 8;                 /* frame count                */
    g_dmaCTRLPKT.ELCNT     = dsize;             /* element count              */
    g_dmaCTRLPKT.ELDOFFSET = 0;                 /* element destination offset */
    g_dmaCTRLPKT.ELSOFFSET = 0;                 /* element source offset      */
    g_dmaCTRLPKT.FRDOFFSET = 0;                 /* frame destination offset   */
    g_dmaCTRLPKT.FRSOFFSET = 0;                 /* frame source offset        */
    g_dmaCTRLPKT.PORTASGN  = 4;                 /* port b                     */
    g_dmaCTRLPKT.RDSIZE    = ACCESS_32_BIT;     /* read size                  */
    g_dmaCTRLPKT.WRSIZE    = ACCESS_32_BIT;     /* write size                 */
    g_dmaCTRLPKT.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
    g_dmaCTRLPKT.ADDMODERD = ADDR_INC1;        /* address mode read          */
    g_dmaCTRLPKT.ADDMODEWR = ADDR_INC1;        /* address mode write         */
    g_dmaCTRLPKT.AUTOINIT  = AUTOINIT_OFF;      /* autoinit                   */
}

void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
    DMA_Comp_Flag = 0x5555AAAA;
}

other functions are generated from halocgen where i have enabled the interrupt for DMA BTC and FTC and CAN 1 IF3 along with other CAN1 High and CAN1 Low interrupts.

With the above code I am having 2 problems-
1.If i give a free run or a step over command, the code gets stuck in phantom interrupt but I am  able to run the code with step into commands.
2. Even when the code runs, I am getting data from only one of the frame (8 bytes) and that too in some different order which gives me a signal that there's something wrong with endianess however I have not changed any addresses manually and it is all generated by halcogen and working fine for features other than DMA.

I have attached the image of transmitted and received data.

can you please help me identify the issue and also suggest me the possible solution for the same?

Thanks
Archana

Part Number: UCD90120A

We have been using the UCD90240 for more years, but as this device has reached EOL, we need to consider the UCD90120A.

The UCD90240 datasheet defines a initialization period (typically 27.5 ms), but if can't find that - for us in a PCIe application - critical information for the UCD90120A device, so please help.

Best Regards

Poul Knudsen
Intel, Denmark

******Cut-and-paste from UCD90240 datasheet ******:

Device Reset
The UCD90240 has an integrated power-on reset (POR) circuit which monitors the supply voltage. At power up,
the POR detects the V33D rise. When V33D is greater than VRESET, the device comes out of reset.
The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic-low
voltage on this pin for longer than tRESET sets the device into reset state. The device comes out of reset within tIRT
after RESET is released to logic-high level.
Any time the device comes out of reset, it begins an initialization routine that lasts typically 27.5 ms 

TWIMC,

I have a customer implementing a custom TDA4M hardware design. They are asking what reference software TI provides for getting customer designed hardware up and running and for programming the QSPI-NOR flash on the first build prototype boards (QSPI-NOR unprogrammed during initial board assembly).

In past generation processors, TI has provided both CodeComposerStudio based reference software for programming QSPI-NOR flash on our EVM's through JTAG and we have generally also provided U-Boot releases for our EVM's that can boot from flash or through Boot ROM peripheral boot modes (ie. USB) and those U-Boot images generally include QSPI-NOR flash drivers that can be used to program QSPI-NOR flash on our EVM's. Source code for both of these options is also generally provided as well so that customers could use either of these reference source code bases and modify them to support the unique QSPI-NOR flash on their custom hardware to generate what they need for initial flash programming support.

The question is what is TI planning for this on Jacinto7/TDA4M devices? What is the status/availability of those tools and if not available immediately when will they become available? Where can customers access the source code for the reference software for the aforementioned (or other) software support TI provides for this purpose? Where can I find procedures for the CodeComposer/JTAG methods? Where can I find procedures for USB peripheral boot mode and using U-Boot to flash custom QSPI-NOR flash memories on customer hardware? What cores are used for programming the QSPI-NOR flash (MCU Island R5F or something else)?

Regards,

Thomas Shelburne

Is there a way(using some bit in a register) to disable automatic RX padding of incoming packets in CPSW hardware

Part Number: TPS62140

Tool/software: WEBENCH® Design Tools

Hello,

I am using TPS62140 buck converter in one of my designs. You can check snap of design as below. All the connections are as mentioned in the datasheet. I simulated the design in Webench, I am getting the results. But when I simulate the same design on TINA, I am not getting the desired results. The output voltage is way less than the desired voltage. Please check below snap from the schematic in TINA.

I performed DV analysis in TINA and results I am getting are much below than desired. Please check below snap.

Desired voltage is 2.5V as per datasheet, whereas I am getting just 33mV. Please help me to resolve this issue.

Regards,

Rewati

Part Number: CC2640R2F

Tool/software: Code Composer Studio

Dear Sir/Madam,

For every compilation, this cc2640r2_oad_offchip_app_FlashROM_oad_merged.bin (App+stack) size is 16MB. This increase in the size is due to repeated 0xFFFF added after actual data.

Due to this, I can't use this file for the OAD. Can anybody help in this regard?

Regards,

Lakshmi

Part Number: TMS320F28335

Tool/software: Code Composer Studio

Hi,

when I compile a project with CCS 8.3.1 I get a compilation error in the abs function:

Invalid arguments. 

When I position the mouse over the error sign in the screen I get  Invalid Arguments Candidates are int abs(int). 

I've check the arguments and they're ok. 

Moreover, the output binary of the project is corrrectly generated.

That's why I think it is not problem of the compiler but a problem that comes from the Eclipse environment.

The error sign I get is different from the error sign  when there is a real error. For example a lack of ; at the end of a line.

Has anyone experienced the same problem ?.

Looks like Eclipse is doing some kind of syntax analysis prior to sending the code to the compiler.

Is there any way to disable this feature of Eclipse ?

Regards,

Aitor

Part Number: PMP40379

Hi,

I am testing PMP40379 board for my project.I wan alternate make for the following listed components.

Regards,

Samruddhi Deshpande

Eaton

Part Number: DAC088S085

Hi sir, 

Please kindly suggest TI best solution to replace below DAC. Customer has cost concern, thanks a lot!

BR, 

Sean Liao

Part Number: CC3220SF-LAUNCHXL

Hi,

My hardware for TIDM-1020 is just CC3220SF LP + CC2640R2F LP + BOOSTXL-SENSORS BP. I read from the document guide that I need to remove and add complements at CC3220SF LP. But from my understanding this for interfacing the Touch Screen BP. So for my 3 hardware connections meaning I do not need to do that?

-kel 

Part Number: IWR6843

I understand this is a very broad question which depends on many things tough.

Do you have any knowledge to share on how this is calculated based on window size for noise estimation, probability of false detection and probability of detection?

We are using CFAR_CASO in range and in doppler CFAR_CA, if that can make  this any easier.

Part Number: DP83867IR

Hi team,

Recently my customer is consulting me if TI has any device or solution to compete with W5500, which do not have much software setting in their MCU, which will save much software resource for them. Thanks. 

Part Number: BQ25895EVM-664

We initially developed our systems using BQ25895 evaluation kit and later on followed the reference design available in the data sheet for BQ25895 evaluation kit manual given at link given at the end (Page 18) to design custom PCB. Also, the picture of schematic for our custom PCB is attached. In the custom PCB, system works fine when powered by a 4V lithium-ion battery at Vbat. We get stable output voltage and are able to communicate with it through the host controller over the I2C. When PCB is powered from the Vbus at 5V through a type C connector, BQ25895 burns down and stops working. Even the BATFET. We have been debugging the issue but haven’t found anything different from the reference design. It simply burns down upon powering up the IC at Vbus with 5 volts. I hope to get some help in the regard. If you need any more details, I shall be providing them. Reference design link (Page 18): http://www.ti.com/lit/ug/sluuba2b/sluuba2b.pdf

Input current at Vbus is limited to 1A max.

Powering up at Vbus using a USB Type-C dedicated connector.

Part Number: CC3100

Hello,

i got the error from above while trying to SL_Connect.

I could not find any desciption of this Problem. Receiving on the same Port from the same device is fine.

Part Number: CC1352R

Hi,

I am working on the Project Zero example. I would like to periodically read the values on two ADCs, and be responsive to UART messaging.
Currently my challenge is determining what the best threading structure is for this project. I have played with both Tasks and Swis, but I am not sure yet. With the Swi, I send an event to the Project Zero task, which calls a function to handle the ADC reading. Likewise, I tried replacing the Swi -> event -> function sequence by creating an extra task with priority 1 lower than that of the Project Zero task, and this new task sleeps between readings. However, then the device is no longer connectable.

So the current status is I have not even implemented the UART, but already the system is lacking in responsiveness.

Any suggestions? I would greatly appreciate it.