Part Number:TPA3251
Hi
We design a active speaker with TPA3251. We want to output 2x140W at 4 Ohm load and THD+N is 1%. But it can only output 100W per channel when the PVDD is 36V and when ever the level of input signal . we use the AP equipment.
When TPA3251 is changed to TPA3255, output power is 120W/ch. we don't find the reason. Can you help to check the schematic as below ? thanks
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Part Number:PROCESSOR-SDK-AM65X
Tool/software: Linux
Hi
i am trying to add multiple dtbo not sure how to do this? In the env there is one defined but cna i just add another name or i have to combine into one DTBO? if i have to combine into one dtbo can you let me know the commnads that i need to execute on m ylinux machine to combine them?
name_overlays=k3-am654-pcie-usb2.dtbo
Thanks
Part Number:MSP432E411Y
Tool/software: Code Composer Studio
I suspect that the immediate bus fault and the linker warning "warning #10247-D: creating output section ".vtable" without a SECTIONS specification" are related. The crash occurs during the C initialization where the zeroed out RAM gets accomplished. It is a bus fault that sends me to the HWI exception handler long before reaching main().
I have looked everywhere in my project as well as the CCS and the Sysconfig Out of the Box demos and cannot figure out where the .vtable issue is coming from. My builds were working just fine until I started removing warnings from various NDK and RTOS files for declared but unused variables and functions.
All of the files build without errors and the linker spits out a more or less correct binary.
I should learn to follow the advice of "never optimize early" . After 40 years of doing this you would think I would learn :-)
Words of wisdom desired. Where should I look to find where the .vtable is generated? I don't even see a .vtable in the examples.
Part Number:BQ40Z50-R2
We are using a bq40z50-r2 embedded inside a removable battery pack. The battery pack will be plugged/unplugged live back and forth from the application device to the battery charger.
SMBus communication and BTP are active in both cases.
Is there any protection needed for the bq40z50-r2?
Part Number:TMS570LS3137
Hello everyone!
I'm having issues with SCI transfers over DMA in my application. I'm using SCI over DMA as a logger and I'm spitting out quite a bit of data. When I do consecutive calls to the logger to write data over DMA, I typically only see the last message fully come out of the SCI module. Whenever I'm logging something, I create a buffer and then send a pointer to that buffer as well as the length to the SendOverDma function which configures the DMA transfer:
SendOverDma(char * buffer, uint32_t length)
{
uint32 sciTxData;
g_dmaCTRL g_dmaCTRLPKT1;
/*Initialize SCI*/
sciInit();
while (((sciREG->FLR & SCI_TX_INT) == 0U) || ((sciREG->FLR & 0x4) == 0x4))
{
} /* Wait */
/*Assign DMA request SCI transmit to Channel 0*/
dmaReqAssign(DMA_CH0, DMA_REQ);
sciTxData = ((uint32_t)(&(sciREG->TD)) + 3);
/*Configure control packet for Channel 0*/
g_dmaCTRLPKT1.SADD = (uint32_t)buffer; /* source address */
g_dmaCTRLPKT1.DADD = sciTxData; /* destination address */
g_dmaCTRLPKT1.CHCTRL = 0; /* channel control */
g_dmaCTRLPKT1.FRCNT = length; /* frame count */
g_dmaCTRLPKT1.ELCNT = 1; /* element count */
g_dmaCTRLPKT1.ELDOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.ELSOFFSET = 0; /* element destination offset */
g_dmaCTRLPKT1.FRDOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.FRSOFFSET = 0; /* frame destination offset */
g_dmaCTRLPKT1.PORTASGN = 4;
g_dmaCTRLPKT1.RDSIZE = ACCESS_8_BIT; /* read size */
g_dmaCTRLPKT1.WRSIZE = ACCESS_8_BIT; /* write size */
g_dmaCTRLPKT1.TTYPE = FRAME_TRANSFER; /* transfer type */
g_dmaCTRLPKT1.ADDMODERD = ADDR_INC1; /* address mode read */
g_dmaCTRLPKT1.ADDMODEWR = ADDR_FIXED; /* address mode write */
g_dmaCTRLPKT1.AUTOINIT = AUTOINIT_OFF; /* autoinit */
/*Set control packet for channel 0 and 1*/
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT1);
/*Set dma channel 0 to trigger on hardware request*/
dmaSetChEnable(DMA_CH0, DMA_HW);
/*Enable DMA*/
dmaEnable();
/*Enable SCI Transmit and Receive DMA Request*/
sciREG->SETINT = (1<<16);
}If consecutive calls are too close to one another in time, then I typically only see the last string get fully transferred, and only one garbled character from the previous message. Am I setting up the DMA transfers incorrectly? Do I need to buffer the messages? Should I wait for an event before transmitting a new message? I thought the following takes care of the waiting:
while (((sciREGx->FLR & SCI_TX_INT) == 0U) || ((sciREGx->FLR & 0x4) == 0x4))
{
} /* Wait */Please help me figure out what's wrong. Thanks in advanced for you help!
Part Number:DS90UB941AS-Q1
Tool/software: Linux
I use a 941 chip ,and have some questions
1. when cpu have no mipi output, some of our board cannot communication with the remote chip with back channel. I2C & remote GPIO not work.(the ratio is 20%),when mipi output is ready, all of them can use back channel. so when cpu have no output I try to use internal clock and enable test pattern to use i2c to control the remote chip, It also work. so to use back channel, must have video data on fpd?
2.when I use internal clock on&off test pattern will trigger a INTB interrupt(I set the 0xC6=0x41),but on UB947 on/off test pattern will not trigger HPD, they are different? to avoid this interrupt I try to set 0xC6 =0x00 when
I enable&disable test pattern,but the interrput still occur, It seems I can't mask it.why?
3, I set REM_INTB_CTRL 0x30 = 0x0A, but re_intb pin still have a falling edge when remote deserializer have interrupt, so the config means GPIO pins will mirror the re_intb pin, and re_intb still work?
4. in 2:2 mode, once one port have locked a link, then another port locked a link will not trigger a HPD interrupt. Can 941 to make port0/port1 HPD independent?
Thanks.
B&R
Enson Liu
Part Number:TMS320F280049C
Hi,
Working on an issue where a SW critical region is entered based on an extsynci input and need to minimize absolute delay to ePWM1's next sync'd edge. The goal is to contain the overall critical region period with some headroom.
Have tried a couple of different pieces of HW and also basic setups (ePWM2_out->GPIO4->Inputxbar5->ExtsyncI->ePWM1 sync). Empirically, it appears that the delay is approx. 80nSec (from synci to sync'd edge of PWM output). Double checked clock dividers in PWM module, tried various input qualification settings (and each one worked as expected adding the anticipated number of cycles from async to sync to 3 to 6 cycles). Based on data manual/TRM I was expecting something in the 3-4 sysclk range with everything accounted for (min extsynci delay, input qual, Tpd's internally, etc). However, it seems to be in the 7-8 sysclk range. Note using T1 does improve things by a cycle or so. In one of the scenarios, HR was disabled, suspecting duty cycle limitation could be at play somehow. But no change in delay.
Looking for a detailed explanation of expected delays in this context. What is the configuration which will produce the shortest delay? What is that expected delay value?
Thanks,
Eric
Part Number:TM4C123GH6PM
Tool/software: Code Composer Studio
Hello everyone. I'm trying to create three PWM waves in CCS. Initially, the PWM wave is with 20% duty cycle; then when pressing and releasing SW1 it has to turn to 40% and when doing the same with SW2 it should turn to 80%. The "main.c" file compiles but in the debugging section it shows me "Error: Unable to read". What may be wrong with my code? All help Will be welcome.
PD: Some comments and functions are in Spanish language (I'm from Peru)
#include <stdint.h>
#include "tm4c123gh6pm.h"
#define SYS_CTRL_RCC (*((volatile unsigned long*)0x400FE060))
#define SYS_CTRL_RCGC0 (*((volatile unsigned long*)0x400FE100))
#define SYS_CTRL_RCGC2 (*((volatile unsigned long*)0x400FE108))
#define SYS_CTRL_RCGCADC (*((volatile unsigned long*)0x400FE638))
#define SYS_CTRL_PRGPIO (*((volatile unsigned long*)0x400FEA08))
#define SYS_CTRL_RCGCGPIO (*((volatile unsigned long*)0x400FE608))
#define SYS_CTRL_GPIOHBCTL (*((volatile unsigned long*)0x400FE06C))
//************************************************************************************************
//-------------------------GPIO PORTB REGISTERS---------------------------------------------------
//************************************************************************************************
#define GPIO_PORTB_DATA (*((volatile unsigned long*)0x400053FC))
#define GPIO_PORTB_DIR (*((volatile unsigned long*)0x40005400))
#define GPIO_PORTB_DEN (*((volatile unsigned long*)0x4000551C))
#define GPIO_PORTB_AFSEL (*((volatile unsigned long*)0x40005420))
#define GPIO_PORTB_PCTL (*((volatile unsigned long*)0x4000552C))
#define GPIO_PORTB_AMSEL (*((volatile unsigned long*)0x40005528))
#define SYS_CTRL_RCGC2_GPIOB 0x00000002
//************************************************************************************************
//-------------------------GPIO PORTF REGISTERS---------------------------------------------------
//************************************************************************************************
#define GPIO_PORTF_DATA (*((volatile unsigned long*)0x400253FC))
#define GPIO_PORTF_DIR (*((volatile unsigned long*)0x40025400))
#define GPIO_PORTF_DEN (*((volatile unsigned long*)0x4002551C))
#define GPIO_PORTF_AFSEL (*((volatile unsigned long*)0x40025420))
//************************************************************************************************
//-------------------------GPIO PORTE REGISTERS---------------------------------------------------
//************************************************************************************************
#define GPIO_PORTE_DATA (*((volatile unsigned long*)0x400243FC))
#define GPIO_PORTE_DIR (*((volatile unsigned long*)0x40024400))
#define GPIO_PORTE_DEN (*((volatile unsigned long*)0x4002451C))
#define GPIO_PORTE_AFSEL (*((volatile unsigned long*)0x40024420))
#define GPIO_PORTE_AMSEL (*((volatile unsigned long*)0x40024528))
//*************************************************************************************************
//------------------------PWM REGISTER-------------------------------------------------------------
//*************************************************************************************************
#define PWM_CTL_R (*((volatile unsigned long *)0x40028000))
#define PWM_SYNC_R (*((volatile unsigned long *)0x40028004))
#define PWM_ENABLE_R (*((volatile unsigned long *)0x40028008))
#define PWM_INVERT_R (*((volatile unsigned long *)0x4002800C))
#define PWM_FAULT_R (*((volatile unsigned long *)0x40028010))
#define PWM_INTEN_R (*((volatile unsigned long *)0x40028014))
#define PWM_RIS_R (*((volatile unsigned long *)0x40028018))
#define PWM_MISC_R (*((volatile unsigned long *)0x4002801C))
#define PWM_STATUS_R (*((volatile unsigned long *)0x40028020))
#define PWM_FAULTVAL_R (*((volatile unsigned long *)0x40028024))
#define PWM_ENUPD_R (*((volatile unsigned long *)0x40028028))
#define PWM0_CTL_R (*((volatile unsigned long *)0x40028040))
#define PWM0_INTEN_R (*((volatile unsigned long *)0x40028044))
#define PWM0_RIS_R (*((volatile unsigned long *)0x40028048))
#define PWM0_ISC_R (*((volatile unsigned long *)0x4002804C))
#define PWM0_LOAD_R (*((volatile unsigned long *)0x40028050))
#define PWM0_COUNT_R (*((volatile unsigned long *)0x40028054))
#define PWM0_CMPA_R (*((volatile unsigned long *)0x40028058))
#define PWM0_CMPB_R (*((volatile unsigned long *)0x4002805C))
#define PWM0_GENA_R (*((volatile unsigned long *)0x40028060))
#define PWM0_GENB_R (*((volatile unsigned long *)0x40028064))
#define PWM0_DBCTL_R (*((volatile unsigned long *)0x40028068))
#define PWM0_DBRISE_R (*((volatile unsigned long *)0x4002806C))
#define PWM0_DBFALL_R (*((volatile unsigned long *)0x40028070))
#define PWM0_FLTSRC0_R (*((volatile unsigned long *)0x40028074))
#define PWM0_FLTSRC1_R (*((volatile unsigned long *)0x40028078))
#define PWM0_MINFLTPER_R (*((volatile unsigned long *)0x4002807C))
//*************************************************************************************************
//------------------------ADC REGISTER-------------------------------------------------------------
//*************************************************************************************************
#define ADC_ACTSS_R (*((volatile unsigned long *)0x40038000))
#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004))
#define ADC0_IM_R (*((volatile unsigned long *)0x40038008))
#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C))
#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014))
#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020))
#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028))
#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x40038048))
#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select mask
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
#define ADC_SSPRI_SS3_4TH 0x00003000 // fourth priority
#define ADC_SSPRI_SS2_3RD 0x00000200 // third priority
#define ADC_SSPRI_SS1_2ND 0x00000010 // second priority
#define ADC_SSPRI_SS0_1ST 0x00000000 // first priority
#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
#define ADC_SSMUX3_MUX0_M 0x00000003 // 1st Sample Input Select mask
#define ADC_SSMUX3_MUX0_S 0 // 1st Sample Input Select lshift
#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data mask
//*************************************************************************************************
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100)) // IRQ 0 to 31 Set Enable Register
#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410)) // IRQ 16 to 19 Priority Register
#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration,
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_CTL_TAEN 0x00000001 // GPTM TimerA Enable
#define TIMER_IMR_TATOIM 0x00000001 // GPTM TimerA Time-Out Interrupt
// Mask
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM TimerA Time-Out Raw
// Interrupt
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load
// Register Low
#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
#define SYSCTL_RCGC1_TIMER0 0x00010000 // timer 0 Clock Gating Control
#define SYS_CTRL_RCGC2_GPIOF 0x00000020
//****************************************************************************************************
//--------------RUN MODE CLOCK CONFIGURATION REGISTER (RCC) BITS DEFINITION---------------------------
//****************************************************************************************************
#define ACG 0x08000000;//Automatic Clock Gating Bit,
#define SYS_DIV 0x07800000;//Clock Divisor.As we are using PLL so MINSYSDIV used as SYS_DIV
#define USESYSDIV 0x00400000;//System Clock Divider
#define USEPWMDIV 0x00100000;//Divsion of clock on PWM clock source.
#define PWMDIV 0x000E0000;//PWM Frequency Division.
#define PWRDN 0x00002000;//Clock in POWER DOWN .
#define BYPASS 0x00000800;//PLL BYPASS bit.
#define XTAL 0x000007C0;//Crystal Oscillator value.
#define OSCSRC 0x00000030;//Oscillator Source Bit.
#define MOSCDIS 0x00000001;//Main Oscillator Disable Bit.
#define ADC_MODE0 0x00000001;
#define ADC_MODE1 0x00000002;
#define TM4C123_SW1 1<<4 // Conectado a PF4
#define TM4C123_SW2 1<<0 // Conectado a PF0
#define TWAIT 400000
#define TON 800000
void Pin_PB6_Config(void); //PB6 M0PWM0 inicialización de pines
void PWM0_EstadoInicial(void);
void config_SW1_TM4C123(void);
void config_SW2_TM4C123(void);
uint8_t lectura_sw1_tm4c123(void);
uint8_t lectura_sw2_tm4c123(void);
void PWM0_EstadoSW1(void);
void PWM0_EstadoSW2(void);
//**************************************************************************************************
//Global Flags
//**************************************************************************************************
void main(void){
void config_pines();
while(1){
if(lectura_sw1_tm4c123()){
PWM0_EstadoSW1(); // si SW1 se pulsa, la onda PWM sera de 40% DC
while(1){
if(lectura_sw2_tm4c123()){
PWM0_EstadoSW2(); // si SW2 se pulsa, la onda PWM sera de 80% DC
break;
}
}
}
}
}
void config_pines(void){
config_SW1_TM4C123();
config_SW2_TM4C123();
Pin_PB6_Config();
}
void Pin_PB6_Config(void){ //configuración pin PB6
SYS_CTRL_RCGC0|=0x00100000;//Enable PWM Clock
SYS_CTRL_PRGPIO|=(SYS_CTRL_RCGC2_GPIOB);//Enable Clock to PORTB
SYS_CTRL_RCGC2|=(SYS_CTRL_RCGC2_GPIOB);//Enable Clock to PORTB
GPIO_PORTB_AFSEL|=(0x00000040);//Enable Alternate Function on PB6
GPIO_PORTB_PCTL&=~0x0F000000;//PORT MUX CONTROL 6
GPIO_PORTB_PCTL|=0x04000000;//PORT MUX CONTROL 6
GPIO_PORTB_AMSEL&=~0x40;//Disable Analogue Functionality
SYS_CTRL_RCC|=0x00100000|(SYS_CTRL_RCC &(~0x000E0000));//Use PWMDIV, DIV_2, BYPASS=0,
GPIO_PORTB_DIR|=0x0000000F;//Make Output
GPIO_PORTB_DEN|=0x000000FF;// Digital Data is Enabled
}
void PWM0_EstadoInicial(void){ //definimos PWM con 20% DC (inicial)
// void config_timer_default(void){ // Configuración Timer 20% DC
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0; // activamos reloj del TIMER0
// SYSCTL_RCGCTIMER_R |= (1<<0); // activamos reloj del TIMER0
while(!(SYSCTL_PRTIMER_R & SYSCTL_PRTIMER_R0));//{
//SYSCTL_PRTIMER_R |= SYSCTL_PRTIMER_R0; // ponemos a 1 el bit correspondiente al registro (para TIMER0 es R0)
//}
TIMER0_CTL_R &= ~(1<<0); //deshabilitar timer A
TIMER0_CFG_R = (TIMER0_CFG_R & ~0x07) + 0x04; // modo 16 bits
TIMER0_TAMR_R = (TIMER0_TAMR_R & ~0xFFF) + 0x50A; // configuración timer A
TIMER0_CTL_R |= (1<<6); // TAPWML = 0
TIMER0_TAILR_R = (TIMER0_TAILR_R & ~(0xFFFF))|39;
TIMER0_TAPR_R = (TIMER0_TAPR_R & ~0xFF);
TIMER0_TAMATCHR_R = (TIMER0_TAMATCHR_R & ~(0xFFFF))|19;
//TIMER0_TAPMR_R =(TIMER0_TAPMR_R & ~0xFF);
}
void PWM0_EstadoSW1(void){ //definimos PWM con 40% DC (SW1)
//void config_timer_default(void){ // Configuración Timer 20% DC
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0; // activamos reloj del TIMER0
// SYSCTL_RCGCTIMER_R |= (1<<0); // activamos reloj del TIMER0
while(!(SYSCTL_PRTIMER_R & SYSCTL_PRTIMER_R0)); // ponemos a 1 el bit correspondiente al registro (para TIMER0 es R0)
TIMER0_CTL_R &= ~(1<<0); //deshabilitar timer A
TIMER0_CFG_R = (TIMER0_CFG_R & ~0x07) + 0x04; // modo 16 bits
TIMER0_TAMR_R = (TIMER0_TAMR_R & ~0xFFF) + 0x50A; // configuración timer A
TIMER0_CTL_R |= (1<<6); // TAPWML = 0
TIMER0_TAILR_R = (TIMER0_TAILR_R & ~(0xFFFF))|59;
TIMER0_TAPR_R = (TIMER0_TAPR_R & ~0xFF);
TIMER0_TAMATCHR_R = (TIMER0_TAMATCHR_R & ~(0xFFFF))|39;
//TIMER0_TAPMR_R =(TIMER0_TAPMR_R & ~0xFF);
}
void PWM0_EstadoSW2(void){ //definimos PWM con 80% DC (SW2)
//void config_timer_default(void){ // Configuración Timer 20% DC
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0; // activamos reloj del TIMER0
// SYSCTL_RCGCTIMER_R |= (1<<0); // activamos reloj del TIMER0
while(!(SYSCTL_PRTIMER_R & SYSCTL_PRTIMER_R0)); // ponemos a 1 el bit correspondiente al registro (para TIMER0 es R0)
TIMER0_CTL_R &= ~(1<<0); //deshabilitar timer A
TIMER0_CFG_R = (TIMER0_CFG_R & ~0x07) + 0x04; // modo 16 bits
TIMER0_TAMR_R = (TIMER0_TAMR_R &~0xFFF) + 0x50A; // configuración timer A
TIMER0_CTL_R |= (1<<6); // TAPWML = 0
TIMER0_TAILR_R = (TIMER0_TAILR_R & ~(0xFFFF))|99;
TIMER0_TAPR_R = (TIMER0_TAPR_R & ~0xFF);
TIMER0_TAMATCHR_R = (TIMER0_TAMATCHR_R & ~(0xFFFF))|79;
TIMER0_TAPMR_R =(TIMER0_TAPMR_R & ~0xFF);
}
void config_SW1_TM4C123(void){
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;
asm(" nop");
asm(" nop");
asm(" nop");
while(!(SYSCTL_PRGPIO_R & SYSCTL_PRGPIO_R5));
GPIO_PORTF_DIR_R &= ~(TM4C123_SW1);
GPIO_PORTF_PUR_R |= (TM4C123_SW1);
GPIO_PORTF_DEN_R |= (TM4C123_SW1);
GPIO_PORTF_PCTL_R &= ~(0x0F);
GPIO_PORTF_PCTL_R |= 0x07;
}
void config_SW2_TM4C123(void){
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;
asm(" nop");
asm(" nop");
asm(" nop");
while(!(SYSCTL_PRGPIO_R & SYSCTL_PRGPIO_R5));
GPIO_PORTF_DIR_R &= ~(TM4C123_SW2);
GPIO_PORTF_LOCK_R = 0x4C4F434B;
GPIO_PORTF_CR_R |= 0x01;
GPIO_PORTF_AFSEL_R &= ~(TM4C123_SW2);
GPIO_PORTF_PUR_R |= (TM4C123_SW2);
GPIO_PORTF_DEN_R |= (TM4C123_SW2);
GPIO_PORTF_PCTL_R &= ~(0x0F);
GPIO_PORTF_PCTL_R |= 0x07;
}
uint8_t lectura_sw1_tm4c123(void){
int contador = 0;
if(!(GPIO_PORTF_DATA_R & TM4C123_SW1)){
for(contador = 0;contador<TWAIT;contador++);
while(!(GPIO_PORTF_DATA_R & TM4C123_SW1));
for(contador = 0;contador<TWAIT;contador++);
return 1;
}
return 0;
}
uint8_t lectura_sw2_tm4c123(void){
int contador = 0;
if(!(GPIO_PORTF_DATA_R & TM4C123_SW2)){
for(contador = 0;contador<TWAIT;contador++);
while(!(GPIO_PORTF_DATA_R & TM4C123_SW2));
for(contador = 0;contador<TWAIT;contador++);
return 1;
}
return 0;
}
Part Number:MSP432P401R
I'm trying to set up my ports for my MSP432 board on Energia. This is my code for configuring the pins:
/*
* Configuring GPIOs (5.1 A4, 5.0 A5, 5.4 A1, 5.5 A0, 4.7 A6)
*/
MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P5,
GPIO_PIN0 | GPIO_PIN1 | GPIO_PIN4 | GPIO_PIN5, GPIO_TERTIARY_MODULE_FUNCTION);
I'm using differential pairing for ports A0 and A1, and then A4 and A5. But when I go into Energia and select ports on the tools tab I can only see A0 and A1. Is there something that I'm missing or that I'm doing wrong?
Thanks
Part Number:BQ40Z80
Hi Team,
Please see below my customer's issue regarding programming bq40z80 samples that we recently shipped. Any idea on what could be happening?:
I created a gg file I pulled off one of my functioning breadboards (An IC I initially pulled off the EVM). When I connect BQ studio to a new Rev04 IC and breadboard, everything communicates. After I import the file to IC, I get not Acks and have major issues with BQ studio and lose all functionality. Attached is my gg file. I’ve also repeated the process on the EVM with a new IC and I have similar issues. I’m assuming the chip is getting bricked somehow. Can you take a look at the gg and see if you see any issues?
Thanks,
Antonio
(Please visit the site to view this file)
Part Number:BQ28Z610
Hello,
I have 2 questions.
1. The series resistor on the VC2 pin for cell balancing is 5 ohm. is there a valid range for this value? if i increase this value do i need to increase the value of resistor on VC1 as well?
2. This IC has just 1 thermistor input. since i am using 2 series cells, i will need to sense the cell temperature for each. is there a comparable part with 2 thermistor inputs or is there a way i can use the TS1 pin and connect 2 thermistors to it (though a mux for example)?
Thanks,
Gaurav
Part Number:BQ24770EVM-540
Angelo, Batt, and all,
Please read the attached document and see the diagram, photo and screenshots. I need help in getting my NVDC Charger / Gauge Evaluation setup working. Right now I'm stuck. Although I'm now able to write and read the registers, I'm not able to get the bq24770EVM-540 to charge or discharge my battery pack. Please let me know your suggestions for my next steps. Thanks,
Carl Olen
(Please visit the site to view this file)
Part Number:AM4378
Tool/software: Linux
TISDK version: 4.3.0.5
Linux Version: 4.9.69
I am trying to get the touchscreen working on a custom board and I was getting very erratic pen up event coordinates. I read here that increasing the value of the "ti,charge-delay" property could help with this. I increased the value and it definitely helped, but I was still getting some inconsistent results every once in a while.
I guess my first question is, what is a normal value for the ti,charge-delay property? And secondly, do you have any idea why the driver would be giving these inconsistent results?
Part Number:LM319
My customer is using this device in a window comparator circuit, as part of a high-speed short-circuit sensing application.
The datasheet lists the maximum allowable differential voltage as +/-5V. In a new version of our application, during a short-circuit event, as much as +7.4V could be present across one of the LM319 inputs (one individual device in the dual package). This event would only occur a maximum of 2-3 times throughout the life of the device, and would last for <5 microseconds. We currently have 1kohm of resistance on each input terminal but this could be increased if required.
Is the +/-5V maximum differential input rating based on causing damage to the device, or simply a maximum level which guarantees that the device meets the specifications (eg. input current, response time, etc) listed in the datasheet? Figure 18 in the datasheet seems to suggest that the input currents do not really increase rapidly until 8V differential input (in the positive direction).
Thanks
Viktorija
Part Number:DRV8873S-Q1EVM
Tool/software: Code Composer Studio
I'm wondering if there are no labs for the card DRV8873S that allow to program the card and not only configure it
Part Number:CC2640
Dear TI,
I have to update a project based in BLE stack 2.1.1 so that it connects simultaneoulsy to two devices. The initial project was based in simple ble central project.
Everything works fine when each device is connected separately (I perform an MTU Exchange at startup and I have set MAX_PDU_SIZE=60). But:
Is it possible that the processing of the data of the oximeter (1 * 60 bytes encrypted packet every 300ms) preempts all the CPU or memory resource of the CC2640 ?
Any idea about what I could do to solve the issue ? (should I increase some RAM, or test new connexion parameters ...)
Many thanks
Thierry
Part Number:DAC80508
Hello,
I have a customer that wants to use the DAC80508 with a load potentially as low as 66 Ohm. When the output is at full scale 2.5V, this could result in ~38mA.
I'm confused if this is within the capabilities of the part. The front page says 20mA, the EC table says short circuit current is 30mA on page 8, and this graph shows current capability up to 40mA.
Thank you!
Regards,
Ryan B.
Part Number:ISO124
Hello,
My customer is evaluating ISO124. I received this question:
"This is primarily a unipolar DC signal that we may try to limit to a 0-5 V range. We intend to use this signal to control power output to a load where 0V would represent 0 % power and 5V would represent 100% power. The ISO124 datasheet shows +/- 4.5V minimum for both VS1 (high side supplies) and VS2 (low side supplies). I am trying to find out the maximum amplitude of the signal that can be passed thru the device if I powered both VS1 and VS2 with +/- 5V supplies."
This doesn't look to be a Rail-to-rail amplifier, how much headroom does there need to be on the output?
Thanks,
Michael
